Re: [PATCH v5 26/39] nds32: Device tree support
2018-01-04 3:14 GMT+08:00 Rob Herring :
> On Tue, Jan 2, 2018 at 2:24 AM, Greentime Hu wrote:
>> From: Greentime Hu
>>
>> This patch adds support for device tree.
>>
>> Signed-off-by: Vincent Chen
>> Signed-off-by: Greentime Hu
>> ---
>> arch/nds32/boot/dts/Makefile |8 +
>> arch/nds32/boot/dts/ae3xx.dts | 73
>> +
>> arch/nds32/kernel/devtree.c | 19 +++
>> 3 files changed, 100 insertions(+)
>> create mode 100644 arch/nds32/boot/dts/Makefile
>> create mode 100644 arch/nds32/boot/dts/ae3xx.dts
>> create mode 100644 arch/nds32/kernel/devtree.c
>>
>> diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
>> new file mode 100644
>> index 000..d31faa8
>> --- /dev/null
>> +++ b/arch/nds32/boot/dts/Makefile
>> @@ -0,0 +1,8 @@
>> +ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
>> +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
>> +else
>> +BUILTIN_DTB :=
>> +endif
>> +obj-$(CONFIG_OF) += $(BUILTIN_DTB)
>> +
>> +clean-files := *.dtb *.dtb.S
>> diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
>> new file mode 100644
>> index 000..6b23d60
>> --- /dev/null
>> +++ b/arch/nds32/boot/dts/ae3xx.dts
>> @@ -0,0 +1,73 @@
>> +/dts-v1/;
>> +/ {
>> + compatible = "andestech,ae3xx";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-parent = <&intc>;
>> +
>> + chosen {
>> + stdout-path = &serial0;
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x 0x4000>;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu@0 {
>> + device_type = "cpu";
>> + compatible = "andestech,n13", "andestech,nds32v3";
>> + reg = <0>;
>> + clock-frequency = <6000>;
>> + next-level-cache = <&L2>;
>> + };
>> + };
>> +
>> + L2: l2-cache@e050 {
>> + compatible = "andestech,atl2c";
>> + reg = <0xe050 0x1000>;
>> + cache-unified;
>> + cache-level = <2>;
>> + };
>> +
>> + apb: clk@0 {
>
> unit address without reg is not valid. Drop the "@0".
>
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <3000>;
>> + };
>> +
>> +
>> + intc: interrupt-controller {
>> + compatible = "andestech,ativic32";
>> + #interrupt-cells = <1>;
>> + interrupt-controller;
>> + };
>> +
>> + serial0: serial@f030 {
>
> All the memory mapped peripherals should be under at least one simple-bus
> node.
>
>> + compatible = "andestech,uart16550", "ns16550a";
>> + reg = <0xf030 0x1000>;
>> + interrupts = <8>;
>> + clock-frequency = <14745600>;
>> + reg-shift = <2>;
>> + reg-offset = <32>;
>> + no-loopback-test = <1>;
>> + };
>> +
>> + timer0: timer@f040 {
>> + compatible = "andestech,atcpit100";
>> + reg = <0xf040 0x1000>;
>> + interrupts = <2>;
>> + clocks = <&apb>;
>> + clock-names = "PCLK";
>> + };
>> +
>> + mac0: mac@e010 {
>
> ethernet@...
>
Hi, Rob:
I'd like to modify it like this in the next version patch.
clock: clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <3000>;
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
serial0: serial@f030 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0xf030 0x1000>;
interrupts = <8>;
clock-frequency = <14745600>;
reg-shift = <2>;
reg-offset = <32>;
no-loopback-test = <1>;
};
timer0: timer@f040 {
compatible = "andestech,atcpit100";
reg = <0xf040 0x1000>;
interrupts = <2>;
clocks = <&clock>;
clock-names = "PCLK";
};
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
L2: cache-controller@e050 {
compatible = "andestech,atl2c";
reg = <0xe050 0x1000>;
Re: [PATCH v5 26/39] nds32: Device tree support
On Tue, Jan 2, 2018 at 2:24 AM, Greentime Hu wrote:
> From: Greentime Hu
>
> This patch adds support for device tree.
>
> Signed-off-by: Vincent Chen
> Signed-off-by: Greentime Hu
> ---
> arch/nds32/boot/dts/Makefile |8 +
> arch/nds32/boot/dts/ae3xx.dts | 73
> +
> arch/nds32/kernel/devtree.c | 19 +++
> 3 files changed, 100 insertions(+)
> create mode 100644 arch/nds32/boot/dts/Makefile
> create mode 100644 arch/nds32/boot/dts/ae3xx.dts
> create mode 100644 arch/nds32/kernel/devtree.c
>
> diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
> new file mode 100644
> index 000..d31faa8
> --- /dev/null
> +++ b/arch/nds32/boot/dts/Makefile
> @@ -0,0 +1,8 @@
> +ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
> +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
> +else
> +BUILTIN_DTB :=
> +endif
> +obj-$(CONFIG_OF) += $(BUILTIN_DTB)
> +
> +clean-files := *.dtb *.dtb.S
> diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
> new file mode 100644
> index 000..6b23d60
> --- /dev/null
> +++ b/arch/nds32/boot/dts/ae3xx.dts
> @@ -0,0 +1,73 @@
> +/dts-v1/;
> +/ {
> + compatible = "andestech,ae3xx";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&intc>;
> +
> + chosen {
> + stdout-path = &serial0;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x 0x4000>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "andestech,n13", "andestech,nds32v3";
> + reg = <0>;
> + clock-frequency = <6000>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + L2: l2-cache@e050 {
> + compatible = "andestech,atl2c";
> + reg = <0xe050 0x1000>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + apb: clk@0 {
unit address without reg is not valid. Drop the "@0".
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <3000>;
> + };
> +
> +
> + intc: interrupt-controller {
> + compatible = "andestech,ativic32";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> +
> + serial0: serial@f030 {
All the memory mapped peripherals should be under at least one simple-bus node.
> + compatible = "andestech,uart16550", "ns16550a";
> + reg = <0xf030 0x1000>;
> + interrupts = <8>;
> + clock-frequency = <14745600>;
> + reg-shift = <2>;
> + reg-offset = <32>;
> + no-loopback-test = <1>;
> + };
> +
> + timer0: timer@f040 {
> + compatible = "andestech,atcpit100";
> + reg = <0xf040 0x1000>;
> + interrupts = <2>;
> + clocks = <&apb>;
> + clock-names = "PCLK";
> + };
> +
> + mac0: mac@e010 {
ethernet@...
> + compatible = "andestech,atmac100";
> + reg = <0xe010 0x1000>;
> + interrupts = <18>;
> + };
> +
> +};
> diff --git a/arch/nds32/kernel/devtree.c b/arch/nds32/kernel/devtree.c
> new file mode 100644
> index 000..bdce0fe
> --- /dev/null
> +++ b/arch/nds32/kernel/devtree.c
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (C) 2005-2017 Andes Technology Corporation
> +
> +#include
> +#include
> +#include
> +
> +void __init early_init_devtree(void *params)
> +{
> + if (!params || !early_init_dt_scan(params)) {
> + pr_crit("\n"
> + "Error: invalid device tree blob at (virtual address
> 0x%p)\n"
> + "\nPlease check your bootloader.", params);
> +
> + BUG_ON(1);
> + }
> +
> + dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
> +}
> --
> 1.7.9.5
>
[PATCH v5 26/39] nds32: Device tree support
From: Greentime Hu
This patch adds support for device tree.
Signed-off-by: Vincent Chen
Signed-off-by: Greentime Hu
---
arch/nds32/boot/dts/Makefile |8 +
arch/nds32/boot/dts/ae3xx.dts | 73 +
arch/nds32/kernel/devtree.c | 19 +++
3 files changed, 100 insertions(+)
create mode 100644 arch/nds32/boot/dts/Makefile
create mode 100644 arch/nds32/boot/dts/ae3xx.dts
create mode 100644 arch/nds32/kernel/devtree.c
diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
new file mode 100644
index 000..d31faa8
--- /dev/null
+++ b/arch/nds32/boot/dts/Makefile
@@ -0,0 +1,8 @@
+ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
+else
+BUILTIN_DTB :=
+endif
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+
+clean-files := *.dtb *.dtb.S
diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
new file mode 100644
index 000..6b23d60
--- /dev/null
+++ b/arch/nds32/boot/dts/ae3xx.dts
@@ -0,0 +1,73 @@
+/dts-v1/;
+/ {
+ compatible = "andestech,ae3xx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x 0x4000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "andestech,n13", "andestech,nds32v3";
+ reg = <0>;
+ clock-frequency = <6000>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ L2: l2-cache@e050 {
+ compatible = "andestech,atl2c";
+ reg = <0xe050 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ apb: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <3000>;
+ };
+
+
+ intc: interrupt-controller {
+ compatible = "andestech,ativic32";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ serial0: serial@f030 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0xf030 0x1000>;
+ interrupts = <8>;
+ clock-frequency = <14745600>;
+ reg-shift = <2>;
+ reg-offset = <32>;
+ no-loopback-test = <1>;
+ };
+
+ timer0: timer@f040 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf040 0x1000>;
+ interrupts = <2>;
+ clocks = <&apb>;
+ clock-names = "PCLK";
+ };
+
+ mac0: mac@e010 {
+ compatible = "andestech,atmac100";
+ reg = <0xe010 0x1000>;
+ interrupts = <18>;
+ };
+
+};
diff --git a/arch/nds32/kernel/devtree.c b/arch/nds32/kernel/devtree.c
new file mode 100644
index 000..bdce0fe
--- /dev/null
+++ b/arch/nds32/kernel/devtree.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include
+#include
+#include
+
+void __init early_init_devtree(void *params)
+{
+ if (!params || !early_init_dt_scan(params)) {
+ pr_crit("\n"
+ "Error: invalid device tree blob at (virtual address
0x%p)\n"
+ "\nPlease check your bootloader.", params);
+
+ BUG_ON(1);
+ }
+
+ dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
+}
--
1.7.9.5
