Re: [PATCH v5 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
Quoting Taniya Das (2020-08-05 22:23:05)
> On 8/6/2020 1:54 AM, Stephen Boyd wrote:
> >> + .hw = _clk_src.clkr.hw,
> >> + },
> >> + .num_parents = 1,
> >> + .flags = CLK_SET_RATE_PARENT,
> >> + .ops = _branch2_ops,
> >> + },
> >> + },
> >> +};
> >> +
> >> +static struct clk_regmap *lpass_core_cc_sc7180_clocks[] = {
> >> + [EXT_MCLK0_CLK_SRC] = _mclk0_clk_src.clkr,
> >> + [LPAIF_PRI_CLK_SRC] = _pri_clk_src.clkr,
> >> + [LPAIF_SEC_CLK_SRC] = _sec_clk_src.clkr,
> >> + [CORE_CLK_SRC] = _clk_src.clkr,
> >
> > And all of these, can they have LPASS_ prefix on the defines? Seems
> > like we're missing a namespace otherwise.
> >
>
> These are generated as they are in the HW plan. Do you still think I
> should update them?
>
As long as there aren't going to be conflicts in the clk names I guess
it's OK to do nothing here.
Re: [PATCH v5 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
Hi Stephen,
On 8/6/2020 1:54 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-07-24 09:07:58)
+
+static struct clk_rcg2 core_clk_src = {
+ .cmd_rcgr = 0x1d000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = lpass_core_cc_parent_map_2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "core_clk_src",
Any chance this can get a better name? Something with LPASS prefix?
These are the exact clock names from the hardware plan.
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _rcg2_ops,
+ },
+};
+
[...]
+
+static struct clk_branch lpass_audio_core_sysnoc_mport_core_clk = {
+ .halt_reg = 0x23000,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x23000,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x23000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "lpass_audio_core_sysnoc_mport_core_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = _clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *lpass_core_cc_sc7180_clocks[] = {
+ [EXT_MCLK0_CLK_SRC] = _mclk0_clk_src.clkr,
+ [LPAIF_PRI_CLK_SRC] = _pri_clk_src.clkr,
+ [LPAIF_SEC_CLK_SRC] = _sec_clk_src.clkr,
+ [CORE_CLK_SRC] = _clk_src.clkr,
And all of these, can they have LPASS_ prefix on the defines? Seems
like we're missing a namespace otherwise.
These are generated as they are in the HW plan. Do you still think I
should update them?
+ [LPASS_AUDIO_CORE_EXT_MCLK0_CLK] = _audio_core_ext_mclk0_clk.clkr,
+ [LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK] =
+ _audio_core_lpaif_pri_ibit_clk.clkr,
+ [LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK] =
+ _audio_core_lpaif_sec_ibit_clk.clkr,
+ [LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK] =
+ _audio_core_sysnoc_mport_core_clk.clkr,
+ [LPASS_LPAAUDIO_DIG_PLL] = _lpaaudio_dig_pll.clkr,
+ [LPASS_LPAAUDIO_DIG_PLL_OUT_ODD] = _lpaaudio_dig_pll_out_odd.clkr,
+};
+
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
Re: [PATCH v5 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
Quoting Taniya Das (2020-07-24 09:07:58)
> +
> +static struct clk_rcg2 core_clk_src = {
> + .cmd_rcgr = 0x1d000,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = lpass_core_cc_parent_map_2,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "core_clk_src",
Any chance this can get a better name? Something with LPASS prefix?
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "bi_tcxo",
> + },
> + .num_parents = 1,
> + .ops = _rcg2_ops,
> + },
> +};
> +
[...]
> +
> +static struct clk_branch lpass_audio_core_sysnoc_mport_core_clk = {
> + .halt_reg = 0x23000,
> + .halt_check = BRANCH_HALT,
> + .hwcg_reg = 0x23000,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x23000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "lpass_audio_core_sysnoc_mport_core_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = _clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = _branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap *lpass_core_cc_sc7180_clocks[] = {
> + [EXT_MCLK0_CLK_SRC] = _mclk0_clk_src.clkr,
> + [LPAIF_PRI_CLK_SRC] = _pri_clk_src.clkr,
> + [LPAIF_SEC_CLK_SRC] = _sec_clk_src.clkr,
> + [CORE_CLK_SRC] = _clk_src.clkr,
And all of these, can they have LPASS_ prefix on the defines? Seems
like we're missing a namespace otherwise.
> + [LPASS_AUDIO_CORE_EXT_MCLK0_CLK] =
> _audio_core_ext_mclk0_clk.clkr,
> + [LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK] =
> + _audio_core_lpaif_pri_ibit_clk.clkr,
> + [LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK] =
> + _audio_core_lpaif_sec_ibit_clk.clkr,
> + [LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK] =
> + _audio_core_sysnoc_mport_core_clk.clkr,
> + [LPASS_LPAAUDIO_DIG_PLL] = _lpaaudio_dig_pll.clkr,
> + [LPASS_LPAAUDIO_DIG_PLL_OUT_ODD] =
> _lpaaudio_dig_pll_out_odd.clkr,
> +};
> +
Re: [PATCH v5 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
Quoting Taniya Das (2020-07-24 09:07:58) > The Low Power Audio subsystem clocks are required for Audio client > to be able to request for the clocks and power domains. > > Signed-off-by: Taniya Das > --- Applied to clk-next
[PATCH v5 4/4] clk: qcom: lpass: Add support for LPASS clock controller for SC7180
The Low Power Audio subsystem clocks are required for Audio client
to be able to request for the clocks and power domains.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpasscorecc-sc7180.c | 477 ++
3 files changed, 487 insertions(+)
create mode 100644 drivers/clk/qcom/lpasscorecc-sc7180.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 318c0ad..0bb5261 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -308,6 +308,15 @@ config SC_GCC_7180
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
+config SC_LPASS_CORECC_7180
+ tristate "SC7180 LPASS Core Clock Controller"
+ select SC_GCC_7180
+ help
+ Support for the LPASS(Low Power Audio Subsystem) core clock controller
+ on SC7180 devices.
+ Say Y if you want to use LPASS clocks and power domains of the LPASS
+ core clock controller.
+
config SC_GPUCC_7180
tristate "SC7180 Graphics Clock Controller"
select SC_GCC_7180
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index ae0979b..b5a706b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
+obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o
obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
b/drivers/clk/qcom/lpasscorecc-sc7180.c
new file mode 100644
index 000..e14e631
--- /dev/null
+++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "gdsc.h"
+
+enum {
+ P_BI_TCXO,
+ P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD,
+ P_SLEEP_CLK,
+};
+
+static struct pll_vco fabia_vco[] = {
+ { 24960, 20, 0 },
+};
+
+static const struct alpha_pll_config lpass_lpaaudio_dig_pll_config = {
+ .l = 0x20,
+ .alpha = 0x0,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2067,
+ .test_ctl_val = 0x4000,
+ .test_ctl_hi_val = 0x,
+ .user_ctl_val = 0x5105,
+ .user_ctl_hi_val = 0x4805,
+};
+
+static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
+ [CLK_ALPHA_PLL_TYPE_FABIA] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_CAL_L_VAL] = 0x8,
+ [PLL_OFF_USER_CTL] = 0x0c,
+ [PLL_OFF_USER_CTL_U] = 0x10,
+ [PLL_OFF_USER_CTL_U1] = 0x14,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL_U] = 0x1C,
+ [PLL_OFF_CONFIG_CTL_U1] = 0x20,
+ [PLL_OFF_TEST_CTL] = 0x24,
+ [PLL_OFF_TEST_CTL_U] = 0x28,
+ [PLL_OFF_STATUS] = 0x30,
+ [PLL_OFF_OPMODE] = 0x38,
+ [PLL_OFF_FRAC] = 0x40,
+ },
+};
+
+static struct clk_alpha_pll lpass_lpaaudio_dig_pll = {
+ .offset = 0x1000,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "lpass_lpaaudio_dig_pll",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static const struct clk_div_table
+ post_div_table_lpass_lpaaudio_dig_pll_out_odd[] = {
+ { 0x5, 5 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv lpass_lpaaudio_dig_pll_out_odd = {
+ .offset = 0x1000,
+ .post_div_shift = 12,
+ .post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
+ .num_post_div =
+ ARRAY_SIZE(post_div_table_lpass_lpaaudio_dig_pll_out_odd),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "lpass_lpaaudio_dig_pll_out_odd",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = _lpaaudio_dig_pll.clkr.hw,
+ },
+ .num_parents = 1,
+
