Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout

2021-01-24 Thread Andrew Jeffery



On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
> 
> Signed-off-by: Chia-Wei, Wang 

Using a Witherspoon (AST2500):

Tested-by: Andrew Jeffery 


Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout

2021-01-19 Thread Andrew Jeffery



On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
> 
> Signed-off-by: Chia-Wei, Wang 

Reviewed-by: Andrew Jeffery 


Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout

2021-01-18 Thread Linus Walleij
On Thu, Jan 14, 2021 at 2:17 PM Chia-Wei, Wang
 wrote:

> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang 

Acked-by: Linus Walleij 

I suppose the patches need to go in together. Tell me if you
need me to apply this one patch to the pinctrl tree.

Yours,
Linus Walleij


[PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout

2021-01-14 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.

Signed-off-by: Chia-Wei, Wang 
---
 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c 
b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 0cab4c2576e2..996ebcba4d38 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -60,7 +60,7 @@
 #define COND2  { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
 
 /* LHCR0 is offset from the end of the H8S/2168-compatible registers */
-#define LHCR0  0x20
+#define LHCR0  0xa0
 #define GFX064 0x64
 
 #define B14 0
@@ -2648,14 +2648,19 @@ static struct regmap *aspeed_g5_acquire_regmap(struct 
aspeed_pinmux_data *ctx,
}
 
if (ip == ASPEED_IP_LPC) {
-   struct device_node *node;
+   struct device_node *np;
struct regmap *map;
 
-   node = of_parse_phandle(ctx->dev->of_node,
+   np = of_parse_phandle(ctx->dev->of_node,
"aspeed,external-nodes", 1);
-   if (node) {
-   map = syscon_node_to_regmap(node->parent);
-   of_node_put(node);
+   if (np) {
+   if (!of_device_is_compatible(np->parent, 
"aspeed,ast2400-lpc-v2") &&
+   !of_device_is_compatible(np->parent, 
"aspeed,ast2500-lpc-v2") &&
+   !of_device_is_compatible(np->parent, 
"aspeed,ast2600-lpc-v2"))
+   return ERR_PTR(-ENODEV);
+
+   map = syscon_node_to_regmap(np->parent);
+   of_node_put(np);
if (IS_ERR(map))
return map;
} else
-- 
2.17.1