[PATCH v5 5/6] spmi: document the PMIC arbiter SPMI bindings
Signed-off-by: Josh Cartwright
---
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
new file mode 100644
index 000..a0a5759
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
@@ -0,0 +1,60 @@
+Qualcomm SPMI Controller (PMIC Arbiter)
+
+The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI
+controller with wrapping arbitration logic to allow for multiple on-chip
+devices to control a single SPMI master.
+
+The PMIC Arbiter can also act as an interrupt controller, providing interrupts
+to slave devices.
+
+See spmi.txt for the generic SPMI controller binding requirements for child
+nodes.
+
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+generic interrupt controller binding documentation.
+
+Required properties:
+- compatible : should be "qcom,spmi-pmic-arb".
+- reg-names : should be "core", "intr", "cnfg"
+- reg : register specifiers, must contain:
+ "core" - core registers
+ "intr" - interrupt controller registers
+ "cnfg" - configuration registers
+- #address-cells : must be set to 2
+- #size-cells : must be set to 0
+- qcom,ee : indicates the active Execution Environment identifier (0-5)
+- qcom,channel : which of the PMIC Arb provided channels to use for accesses
(0-5)
+- interrupts : interrupt list for the PMIC Arb controller, must contain a
+ single interrupt entry for the peripheral interrupt
+- interrupt-names : corresponding interrupt names for the interrupts
+listed in the 'interrupts' property, must contain:
+ "periph_irq" - summary interrupt for PMIC peripherals
+- interrupt-controller : boolean indicator that the PMIC arbiter is an
interrupt controller
+- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
+cell 1: slave ID for the requested interrupt (0-15)
+cell 2: peripheral ID for requested interrupt (0-255)
+cell 3: the requested peripheral interrupt (0-7)
+cell 4: interrupt flags indicating level-sense information, as defined in
+dt-bindings/interrupt-controller/irq.h
+
+Example:
+
+ spmi {
+ compatible = "qcom,spmi-pmic-arb";
+ reg-names = "core", "intr", "cnfg";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+
+ interrupt-names = "periph_irq";
+ interrupts = <0 190 0>;
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
--
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[PATCH v5 5/6] spmi: document the PMIC arbiter SPMI bindings
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
new file mode 100644
index 000..a0a5759
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
@@ -0,0 +1,60 @@
+Qualcomm SPMI Controller (PMIC Arbiter)
+
+The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI
+controller with wrapping arbitration logic to allow for multiple on-chip
+devices to control a single SPMI master.
+
+The PMIC Arbiter can also act as an interrupt controller, providing interrupts
+to slave devices.
+
+See spmi.txt for the generic SPMI controller binding requirements for child
+nodes.
+
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+generic interrupt controller binding documentation.
+
+Required properties:
+- compatible : should be qcom,spmi-pmic-arb.
+- reg-names : should be core, intr, cnfg
+- reg : register specifiers, must contain:
+ core - core registers
+ intr - interrupt controller registers
+ cnfg - configuration registers
+- #address-cells : must be set to 2
+- #size-cells : must be set to 0
+- qcom,ee : indicates the active Execution Environment identifier (0-5)
+- qcom,channel : which of the PMIC Arb provided channels to use for accesses
(0-5)
+- interrupts : interrupt list for the PMIC Arb controller, must contain a
+ single interrupt entry for the peripheral interrupt
+- interrupt-names : corresponding interrupt names for the interrupts
+listed in the 'interrupts' property, must contain:
+ periph_irq - summary interrupt for PMIC peripherals
+- interrupt-controller : boolean indicator that the PMIC arbiter is an
interrupt controller
+- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
+cell 1: slave ID for the requested interrupt (0-15)
+cell 2: peripheral ID for requested interrupt (0-255)
+cell 3: the requested peripheral interrupt (0-7)
+cell 4: interrupt flags indicating level-sense information, as defined in
+dt-bindings/interrupt-controller/irq.h
+
+Example:
+
+ spmi {
+ compatible = qcom,spmi-pmic-arb;
+ reg-names = core, intr, cnfg;
+ reg = 0xfc4cf000 0x1000,
+ 0xfc4cb000 0x1000,
+ 0xfc4ca000 0x1000;
+
+ interrupt-names = periph_irq;
+ interrupts = 0 190 0;
+
+ qcom,ee = 0;
+ qcom,channel = 0;
+
+ #address-cells = 2;
+ #size-cells = 0;
+
+ interrupt-controller;
+ #interrupt-cells = 4;
+ };
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
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Please read the FAQ at http://www.tux.org/lkml/
