Re: [PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Mon, 2020-06-29 at 15:53 -0600, Rob Herring wrote: > On Thu, 18 Jun 2020 19:33:32 +0800, Hanks Chen wrote: > > From: Andy Teng > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Signed-off-by: Andy Teng > > --- > > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 > > > > 1 file changed, 210 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dts:21:18: > fatal error: dt-bindings/pinctrl/mt6779-pinfunc.h: No such file or directory > #include > ^~ > compilation terminated. > scripts/Makefile.lib:315: recipe for target > 'Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml' > failed > make[1]: *** > [Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml] > Error 1 > make[1]: *** Waiting for unfinished jobs > Makefile:1347: recipe for target 'dt_binding_check' failed > make: *** [dt_binding_check] Error 2 > > > See https://patchwork.ozlabs.org/patch/1312018 > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master > --upgrade > > Please check and re-submit. > I already ran the dt_binding_check and it looks good. > > > Here, you need patch 2 to come first or merge it into this patch as it > is part of the binding. > I'll merge it into this patch in next version. Thank you for your comment. Hanks > Rob >
Re: [PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Thu, 18 Jun 2020 19:33:32 +0800, Hanks Chen wrote: > From: Andy Teng > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > Signed-off-by: Andy Teng > --- > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 > > 1 file changed, 210 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > My bot found errors running 'make dt_binding_check' on your patch: Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dts:21:18: fatal error: dt-bindings/pinctrl/mt6779-pinfunc.h: No such file or directory #include ^~ compilation terminated. scripts/Makefile.lib:315: recipe for target 'Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml' failed make[1]: *** [Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs Makefile:1347: recipe for target 'dt_binding_check' failed make: *** [dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1312018 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit. Here, you need patch 2 to come first or merge it into this patch as it is part of the binding. Rob
Re: [PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Sun, 2020-06-21 at 23:13 +0200, Pavel Machek wrote: > On Thu 2020-06-18 19:33:32, Hanks Chen wrote: > > From: Andy Teng > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Signed-off-by: Andy Teng > > > > + Pull up setings for 2 pull resistors, R0 and R1. User can > > + configure those special pins. Valid arguments are described > > as below: > > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. > > Typo => disabled. Got it, I'll fix the typo in next version. Thanks! > Pavel >
Re: [PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
On Thu 2020-06-18 19:33:32, Hanks Chen wrote: > From: Andy Teng > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > Signed-off-by: Andy Teng > + Pull up setings for 2 pull resistors, R0 and R1. User can > + configure those special pins. Valid arguments are described as > below: > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. Typo => disabled. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html signature.asc Description: Digital signature
[PATCH v6 1/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
From: Andy Teng Add devicetree bindings for MediaTek MT6779 pinctrl driver. Signed-off-by: Andy Teng --- .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 1 file changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml new file mode 100644 index 000..85819a4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT6779 Pin Controller Device Tree Bindings + +maintainers: + - Andy Teng + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + - compatible: "syscon" + +properties: + compatible: +const: mediatek,mt6779-pinctrl + + reg: +minItems: 9 +maxItems: 9 +description: | + physical address base for gpio-related control registers. + + reg-names: +description: | + GPIO base register names. The names are "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + + gpio-controller: true + + "#gpio-cells": +const: 2 +description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + gpio-ranges: +minItems: 1 +maxItems: 5 +description: | + GPIO valid number range. + + interrupt-controller: true + + interrupts: +maxItems: 1 +description: | + Specifies the summary IRQ. + + "#interrupt-cells": +const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - interrupts + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': +type: object +patternProperties: + '-pins*$': +type: object +description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input schmitt. + +properties: + pinmux: +description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in boot/dts/-pinfunc.h directly. + + bias-disable: +type: boolean + + bias-pull-up: +type: boolean + + bias-pull-down: +type: boolean + + input-enable: +type: boolean + + input-disable: +type: boolean + + output-low: +type: boolean + + output-high: +type: boolean + + input-schmitt-enable: +type: boolean + + input-schmitt-disable: +type: boolean + + mediatek,pull-up-adv: +description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: +description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + drive-strength: +description: | + Selects the drive strength for the specified pins in mA. +allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 +
