Re: [PATCH v6 2/2] clk: uniphier: add clock data for UniPhier SoCs

[Masahiro Yamada]

Hi Stephen,


2016-08-19 9:28 GMT+09:00 Stephen Boyd :

>> +
>> +
>> +System clock
>> +
>> +
>> +Required properties:
>> +- compatible: should be one of the following:
>> +"socionext,uniphier-sld3-clock" - for PH1-sLD3 SoC.
>> +"socionext,uniphier-ld4-clock"  - for PH1-LD4 SoC.
>> +"socionext,uniphier-pro4-clock" - for PH1-Pro4 SoC.
>> +"socionext,uniphier-sld8-clock" - for PH1-sLD8 SoC.
>> +"socionext,uniphier-pro5-clock" - for PH1-Pro5 SoC.
>> +"socionext,uniphier-pxs2-clock" - for ProXstream2/PH1-LD6b SoC.
>> +"socionext,uniphier-ld11-clock" - for PH1-LD11 SoC.
>> +"socionext,uniphier-ld20-clock" - for PH1-LD20 SoC.
>> +- #clock-cells: should be 1.
>> +
>> +Example:
>> +
>> + sysctrl@6184 {
>> + compatible = "socionext,uniphier-ld20-sysctrl",
>> +  "simple-mfd", "syscon";
>> + reg = <0x6184 0x4000>;
>> +
>> + clock {
>> + compatible = "socionext,uniphier-ld20-clock";
>> + #clock-cells = <1>;
>> + };
>> +
>> + other nodes ...
>
> What are the other nodes? Is there a document for the rest of the
> MFD?

At lease there are "clock" and "reset" in this MFD at this point.
Perhaps, I may want to add more in the future.

That's why I do not want to list all of the sibling nodes.

The reset node is documented in its binding document,
added by the following patch:
https://patchwork.kernel.org/patch/9255101/


-- 
Best Regards
Masahiro Yamada

Re: [PATCH v6 2/2] clk: uniphier: add clock data for UniPhier SoCs

[Masahiro Yamada]

Hi Stephen,


2016-08-19 9:28 GMT+09:00 Stephen Boyd :

>> +
>> +
>> +System clock
>> +
>> +
>> +Required properties:
>> +- compatible: should be one of the following:
>> +"socionext,uniphier-sld3-clock" - for PH1-sLD3 SoC.
>> +"socionext,uniphier-ld4-clock"  - for PH1-LD4 SoC.
>> +"socionext,uniphier-pro4-clock" - for PH1-Pro4 SoC.
>> +"socionext,uniphier-sld8-clock" - for PH1-sLD8 SoC.
>> +"socionext,uniphier-pro5-clock" - for PH1-Pro5 SoC.
>> +"socionext,uniphier-pxs2-clock" - for ProXstream2/PH1-LD6b SoC.
>> +"socionext,uniphier-ld11-clock" - for PH1-LD11 SoC.
>> +"socionext,uniphier-ld20-clock" - for PH1-LD20 SoC.
>> +- #clock-cells: should be 1.
>> +
>> +Example:
>> +
>> + sysctrl@6184 {
>> + compatible = "socionext,uniphier-ld20-sysctrl",
>> +  "simple-mfd", "syscon";
>> + reg = <0x6184 0x4000>;
>> +
>> + clock {
>> + compatible = "socionext,uniphier-ld20-clock";
>> + #clock-cells = <1>;
>> + };
>> +
>> + other nodes ...
>
> What are the other nodes? Is there a document for the rest of the
> MFD?

At lease there are "clock" and "reset" in this MFD at this point.
Perhaps, I may want to add more in the future.

That's why I do not want to list all of the sibling nodes.

The reset node is documented in its binding document,
added by the following patch:
https://patchwork.kernel.org/patch/9255101/


-- 
Best Regards
Masahiro Yamada

Re: [PATCH v6 2/2] clk: uniphier: add clock data for UniPhier SoCs

[Stephen Boyd]

On 08/02, Masahiro Yamada wrote:
> diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt 
> b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
> new file mode 100644
> index 000..1a4db8b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
> @@ -0,0 +1,134 @@
> +UniPhier clock controller
> +
> +
> +System clock
> +
> +
> +Required properties:
> +- compatible: should be one of the following:
> +"socionext,uniphier-sld3-clock" - for PH1-sLD3 SoC.
> +"socionext,uniphier-ld4-clock"  - for PH1-LD4 SoC.
> +"socionext,uniphier-pro4-clock" - for PH1-Pro4 SoC.
> +"socionext,uniphier-sld8-clock" - for PH1-sLD8 SoC.
> +"socionext,uniphier-pro5-clock" - for PH1-Pro5 SoC.
> +"socionext,uniphier-pxs2-clock" - for ProXstream2/PH1-LD6b SoC.
> +"socionext,uniphier-ld11-clock" - for PH1-LD11 SoC.
> +"socionext,uniphier-ld20-clock" - for PH1-LD20 SoC.
> +- #clock-cells: should be 1.
> +
> +Example:
> +
> + sysctrl@6184 {
> + compatible = "socionext,uniphier-ld20-sysctrl",
> +  "simple-mfd", "syscon";
> + reg = <0x6184 0x4000>;
> +
> + clock {
> + compatible = "socionext,uniphier-ld20-clock";
> + #clock-cells = <1>;
> + };
> +
> + other nodes ...

What are the other nodes? Is there a document for the rest of the
MFD?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v6 2/2] clk: uniphier: add clock data for UniPhier SoCs

[Stephen Boyd]

On 08/02, Masahiro Yamada wrote:
> diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt 
> b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
> new file mode 100644
> index 000..1a4db8b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
> @@ -0,0 +1,134 @@
> +UniPhier clock controller
> +
> +
> +System clock
> +
> +
> +Required properties:
> +- compatible: should be one of the following:
> +"socionext,uniphier-sld3-clock" - for PH1-sLD3 SoC.
> +"socionext,uniphier-ld4-clock"  - for PH1-LD4 SoC.
> +"socionext,uniphier-pro4-clock" - for PH1-Pro4 SoC.
> +"socionext,uniphier-sld8-clock" - for PH1-sLD8 SoC.
> +"socionext,uniphier-pro5-clock" - for PH1-Pro5 SoC.
> +"socionext,uniphier-pxs2-clock" - for ProXstream2/PH1-LD6b SoC.
> +"socionext,uniphier-ld11-clock" - for PH1-LD11 SoC.
> +"socionext,uniphier-ld20-clock" - for PH1-LD20 SoC.
> +- #clock-cells: should be 1.
> +
> +Example:
> +
> + sysctrl@6184 {
> + compatible = "socionext,uniphier-ld20-sysctrl",
> +  "simple-mfd", "syscon";
> + reg = <0x6184 0x4000>;
> +
> + clock {
> + compatible = "socionext,uniphier-ld20-clock";
> + #clock-cells = <1>;
> + };
> +
> + other nodes ...

What are the other nodes? Is there a document for the rest of the
MFD?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v6 2/2] clk: uniphier: add clock data for UniPhier SoCs

[Masahiro Yamada]

Add clock data arrays for all UniPhier SoCs.

Signed-off-by: Masahiro Yamada 
---

 .../devicetree/bindings/clock/uniphier-clock.txt   | 134 ++
 drivers/clk/uniphier/Makefile  |   3 +
 drivers/clk/uniphier/clk-uniphier-core.c   |  91 +
 drivers/clk/uniphier/clk-uniphier-mio.c| 103 ++
 drivers/clk/uniphier/clk-uniphier-peri.c   |  59 
 drivers/clk/uniphier/clk-uniphier-sys.c| 151 +
 drivers/clk/uniphier/clk-uniphier.h|  13 ++
 7 files changed, 554 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/uniphier-clock.txt
 create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
 create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
 create mode 100644 drivers/clk/uniphier/clk-uniphier-sys.c

diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt 
b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
new file mode 100644
index 000..1a4db8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
@@ -0,0 +1,134 @@
+UniPhier clock controller
+
+
+System clock
+
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   sysctrl@6184 {
+   compatible = "socionext,uniphier-ld20-sysctrl",
+"simple-mfd", "syscon";
+   reg = <0x6184 0x4000>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 8: ST DMAC
+12: GIO (Giga bit stream I/O)
+14: USB3 ch0 host
+15: USB3 ch1 host
+16: USB3 ch0 PHY0
+17: USB3 ch0 PHY1
+20: USB3 ch1 PHY0
+21: USB3 ch1 PHY1
+
+
+Media I/O (MIO) clock
+-
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-mio-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-mio-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-mio-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-mio-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-mio-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-mio-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-mio-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-mio-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   mioctrl@5981 {
+   compatible = "socionext,uniphier-ld20-mioctrl",
+"simple-mfd", "syscon";
+   reg = <0x5981 0x800>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-mio-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 0: SD ch0 host
+ 1: eMMC host
+ 2: SD ch1 host
+ 7: MIO DMAC
+ 8: USB2 ch0 host
+ 9: USB2 ch1 host
+10: USB2 ch2 host
+11: USB2 ch3 host
+12: USB2 ch0 PHY
+13: USB2 ch1 PHY
+14: USB2 ch2 PHY
+15: USB2 ch3 PHY
+
+
+Peripheral clock
+
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-peri-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-peri-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-peri-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-peri-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-peri-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-peri-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-peri-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-peri-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   perictrl@5982 {
+   compatible = "socionext,uniphier-ld20-perictrl",
+"simple-mfd", "syscon";
+   reg = <0x5982 0x200>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-peri-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 0: UART ch0
+ 1: UART ch1
+ 2: UART ch2
+ 3: UART ch3
+ 4: I2C ch0
+ 5: I2C ch1
+ 6: I2C ch2
+ 7: I2C ch3
+ 8: I2C ch4
+ 9: I2C ch5
+10: I2C ch6
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 

[PATCH v6 2/2] clk: uniphier: add clock data for UniPhier SoCs

[Masahiro Yamada]

Add clock data arrays for all UniPhier SoCs.

Signed-off-by: Masahiro Yamada 
---

 .../devicetree/bindings/clock/uniphier-clock.txt   | 134 ++
 drivers/clk/uniphier/Makefile  |   3 +
 drivers/clk/uniphier/clk-uniphier-core.c   |  91 +
 drivers/clk/uniphier/clk-uniphier-mio.c| 103 ++
 drivers/clk/uniphier/clk-uniphier-peri.c   |  59 
 drivers/clk/uniphier/clk-uniphier-sys.c| 151 +
 drivers/clk/uniphier/clk-uniphier.h|  13 ++
 7 files changed, 554 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/uniphier-clock.txt
 create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
 create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
 create mode 100644 drivers/clk/uniphier/clk-uniphier-sys.c

diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt 
b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
new file mode 100644
index 000..1a4db8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
@@ -0,0 +1,134 @@
+UniPhier clock controller
+
+
+System clock
+
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   sysctrl@6184 {
+   compatible = "socionext,uniphier-ld20-sysctrl",
+"simple-mfd", "syscon";
+   reg = <0x6184 0x4000>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 8: ST DMAC
+12: GIO (Giga bit stream I/O)
+14: USB3 ch0 host
+15: USB3 ch1 host
+16: USB3 ch0 PHY0
+17: USB3 ch0 PHY1
+20: USB3 ch1 PHY0
+21: USB3 ch1 PHY1
+
+
+Media I/O (MIO) clock
+-
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-mio-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-mio-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-mio-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-mio-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-mio-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-mio-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-mio-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-mio-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   mioctrl@5981 {
+   compatible = "socionext,uniphier-ld20-mioctrl",
+"simple-mfd", "syscon";
+   reg = <0x5981 0x800>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-mio-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 0: SD ch0 host
+ 1: eMMC host
+ 2: SD ch1 host
+ 7: MIO DMAC
+ 8: USB2 ch0 host
+ 9: USB2 ch1 host
+10: USB2 ch2 host
+11: USB2 ch3 host
+12: USB2 ch0 PHY
+13: USB2 ch1 PHY
+14: USB2 ch2 PHY
+15: USB2 ch3 PHY
+
+
+Peripheral clock
+
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-peri-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-peri-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-peri-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-peri-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-peri-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-peri-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-peri-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-peri-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   perictrl@5982 {
+   compatible = "socionext,uniphier-ld20-perictrl",
+"simple-mfd", "syscon";
+   reg = <0x5982 0x200>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-peri-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 0: UART ch0
+ 1: UART ch1
+ 2: UART ch2
+ 3: UART ch3
+ 4: I2C ch0
+ 5: I2C ch1
+ 6: I2C ch2
+ 7: I2C ch3
+ 8: I2C ch4
+ 9: I2C ch5
+10: I2C ch6
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 8f359aa..6822691 100644
--- 

[PATCH v6 2/2] clk: uniphier: add clock data for UniPhier SoCs

[Masahiro Yamada]

Add clock data arrays for all UniPhier SoCs.

Signed-off-by: Masahiro Yamada 
---

 .../devicetree/bindings/clock/uniphier-clock.txt   | 134 ++
 drivers/clk/uniphier/Makefile  |   3 +
 drivers/clk/uniphier/clk-uniphier-core.c   |  91 +
 drivers/clk/uniphier/clk-uniphier-mio.c| 103 ++
 drivers/clk/uniphier/clk-uniphier-peri.c   |  59 
 drivers/clk/uniphier/clk-uniphier-sys.c| 151 +
 drivers/clk/uniphier/clk-uniphier.h|  13 ++
 7 files changed, 554 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/uniphier-clock.txt
 create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
 create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
 create mode 100644 drivers/clk/uniphier/clk-uniphier-sys.c

diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt 
b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
new file mode 100644
index 000..1a4db8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
@@ -0,0 +1,134 @@
+UniPhier clock controller
+
+
+System clock
+
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   sysctrl@6184 {
+   compatible = "socionext,uniphier-ld20-sysctrl",
+"simple-mfd", "syscon";
+   reg = <0x6184 0x4000>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 8: ST DMAC
+12: GIO (Giga bit stream I/O)
+14: USB3 ch0 host
+15: USB3 ch1 host
+16: USB3 ch0 PHY0
+17: USB3 ch0 PHY1
+20: USB3 ch1 PHY0
+21: USB3 ch1 PHY1
+
+
+Media I/O (MIO) clock
+-
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-mio-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-mio-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-mio-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-mio-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-mio-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-mio-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-mio-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-mio-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   mioctrl@5981 {
+   compatible = "socionext,uniphier-ld20-mioctrl",
+"simple-mfd", "syscon";
+   reg = <0x5981 0x800>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-mio-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 0: SD ch0 host
+ 1: eMMC host
+ 2: SD ch1 host
+ 7: MIO DMAC
+ 8: USB2 ch0 host
+ 9: USB2 ch1 host
+10: USB2 ch2 host
+11: USB2 ch3 host
+12: USB2 ch0 PHY
+13: USB2 ch1 PHY
+14: USB2 ch2 PHY
+15: USB2 ch3 PHY
+
+
+Peripheral clock
+
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-peri-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-peri-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-peri-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-peri-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-peri-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-peri-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-peri-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-peri-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   perictrl@5982 {
+   compatible = "socionext,uniphier-ld20-perictrl",
+"simple-mfd", "syscon";
+   reg = <0x5982 0x200>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-peri-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 0: UART ch0
+ 1: UART ch1
+ 2: UART ch2
+ 3: UART ch3
+ 4: I2C ch0
+ 5: I2C ch1
+ 6: I2C ch2
+ 7: I2C ch3
+ 8: I2C ch4
+ 9: I2C ch5
+10: I2C ch6
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 

[PATCH v6 2/2] clk: uniphier: add clock data for UniPhier SoCs

[Masahiro Yamada]

Add clock data arrays for all UniPhier SoCs.

Signed-off-by: Masahiro Yamada 
---

 .../devicetree/bindings/clock/uniphier-clock.txt   | 134 ++
 drivers/clk/uniphier/Makefile  |   3 +
 drivers/clk/uniphier/clk-uniphier-core.c   |  91 +
 drivers/clk/uniphier/clk-uniphier-mio.c| 103 ++
 drivers/clk/uniphier/clk-uniphier-peri.c   |  59 
 drivers/clk/uniphier/clk-uniphier-sys.c| 151 +
 drivers/clk/uniphier/clk-uniphier.h|  13 ++
 7 files changed, 554 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/uniphier-clock.txt
 create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
 create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
 create mode 100644 drivers/clk/uniphier/clk-uniphier-sys.c

diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt 
b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
new file mode 100644
index 000..1a4db8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
@@ -0,0 +1,134 @@
+UniPhier clock controller
+
+
+System clock
+
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   sysctrl@6184 {
+   compatible = "socionext,uniphier-ld20-sysctrl",
+"simple-mfd", "syscon";
+   reg = <0x6184 0x4000>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 8: ST DMAC
+12: GIO (Giga bit stream I/O)
+14: USB3 ch0 host
+15: USB3 ch1 host
+16: USB3 ch0 PHY0
+17: USB3 ch0 PHY1
+20: USB3 ch1 PHY0
+21: USB3 ch1 PHY1
+
+
+Media I/O (MIO) clock
+-
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-mio-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-mio-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-mio-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-mio-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-mio-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-mio-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-mio-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-mio-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   mioctrl@5981 {
+   compatible = "socionext,uniphier-ld20-mioctrl",
+"simple-mfd", "syscon";
+   reg = <0x5981 0x800>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-mio-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 0: SD ch0 host
+ 1: eMMC host
+ 2: SD ch1 host
+ 7: MIO DMAC
+ 8: USB2 ch0 host
+ 9: USB2 ch1 host
+10: USB2 ch2 host
+11: USB2 ch3 host
+12: USB2 ch0 PHY
+13: USB2 ch1 PHY
+14: USB2 ch2 PHY
+15: USB2 ch3 PHY
+
+
+Peripheral clock
+
+
+Required properties:
+- compatible: should be one of the following:
+"socionext,uniphier-sld3-peri-clock" - for PH1-sLD3 SoC.
+"socionext,uniphier-ld4-peri-clock"  - for PH1-LD4 SoC.
+"socionext,uniphier-pro4-peri-clock" - for PH1-Pro4 SoC.
+"socionext,uniphier-sld8-peri-clock" - for PH1-sLD8 SoC.
+"socionext,uniphier-pro5-peri-clock" - for PH1-Pro5 SoC.
+"socionext,uniphier-pxs2-peri-clock" - for ProXstream2/PH1-LD6b SoC.
+"socionext,uniphier-ld11-peri-clock" - for PH1-LD11 SoC.
+"socionext,uniphier-ld20-peri-clock" - for PH1-LD20 SoC.
+- #clock-cells: should be 1.
+
+Example:
+
+   perictrl@5982 {
+   compatible = "socionext,uniphier-ld20-perictrl",
+"simple-mfd", "syscon";
+   reg = <0x5982 0x200>;
+
+   clock {
+   compatible = "socionext,uniphier-ld20-peri-clock";
+   #clock-cells = <1>;
+   };
+
+   other nodes ...
+   };
+
+Provided clocks:
+
+ 0: UART ch0
+ 1: UART ch1
+ 2: UART ch2
+ 3: UART ch3
+ 4: I2C ch0
+ 5: I2C ch1
+ 6: I2C ch2
+ 7: I2C ch3
+ 8: I2C ch4
+ 9: I2C ch5
+10: I2C ch6
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 8f359aa..6822691 100644
---