Re: [RESEND PATCH v6 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
On 05/12/2020 22:36, Linus Walleij wrote: On Wed, Dec 2, 2020 at 5:35 PM Srinivas Kandagatla wrote: Add initial pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8250. Patch applied! +config PINCTRL_LPASS_LPI + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" + depends on GPIOLIB I added: select PINMUX select PINCONF select GENERIC_PINCONF When applying. You need these I think, your code is working because other drivers are selecting these for you, right? The build robot would hack this to pieces though. Many thanks for doing this! --srini Yours, Linus Walleij
Re: [RESEND PATCH v6 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
On Wed, Dec 2, 2020 at 5:35 PM Srinivas Kandagatla wrote: > Add initial pinctrl driver to support pin configuration for > LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl > on SM8250. Patch applied! > +config PINCTRL_LPASS_LPI > + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" > + depends on GPIOLIB I added: select PINMUX select PINCONF select GENERIC_PINCONF When applying. You need these I think, your code is working because other drivers are selecting these for you, right? The build robot would hack this to pieces though. Yours, Linus Walleij
Re: [RESEND PATCH v6 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
On Wed 02 Dec 10:34 CST 2020, Srinivas Kandagatla wrote:
> Add initial pinctrl driver to support pin configuration for
> LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
> on SM8250.
>
> This IP is an additional pin control block for Audio Pins on top the
> existing SoC Top level pin-controller.
> Hardware setup looks like:
>
> TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
>
> This pin controller has some similarities compared to Top level
> msm SoC Pin controller like 'each pin belongs to a single group'
> and so on. However this one is intended to control only audio
> pins in particular, which can not be configured/touched by the
> Top level SoC pin controller except setting them as gpios.
> Apart from this, slew rate is also available in this block for
> certain pins which are connected to SLIMbus or SoundWire Bus.
>
> Signed-off-by: Srinivas Kandagatla
Let's try again, this time with Linus in Cc :)
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> drivers/pinctrl/qcom/Kconfig | 8 +
> drivers/pinctrl/qcom/Makefile| 1 +
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 +++
> 3 files changed, 704 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 5fe7b8aaf69d..d3e4e89c2810 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -236,4 +236,12 @@ config PINCTRL_SM8250
> Qualcomm Technologies Inc TLMM block found on the Qualcomm
> Technologies Inc SM8250 platform.
>
> +config PINCTRL_LPASS_LPI
> + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
> + depends on GPIOLIB
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> + (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
> +
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 9e3d9c91a444..c8520155fb1b 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
> obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
> obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
> obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
> +obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> new file mode 100644
> index ..369ee20a7ea9
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> @@ -0,0 +1,695 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2020 Linaro Ltd.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "../core.h"
> +#include "../pinctrl-utils.h"
> +
> +#define LPI_SLEW_RATE_CTL_REG0xa000
> +#define LPI_TLMM_REG_OFFSET 0x1000
> +#define LPI_SLEW_RATE_MAX0x03
> +#define LPI_SLEW_BITS_SIZE 0x02
> +#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
> +#define LPI_GPIO_CFG_REG 0x00
> +#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
> +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
> +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
> +#define LPI_GPIO_OE_MASK BIT(9)
> +#define LPI_GPIO_VALUE_REG 0x04
> +#define LPI_GPIO_VALUE_IN_MASK BIT(0)
> +#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
> +
> +#define LPI_GPIO_BIAS_DISABLE0x0
> +#define LPI_GPIO_PULL_DOWN 0x1
> +#define LPI_GPIO_KEEPER 0x2
> +#define LPI_GPIO_PULL_UP 0x3
> +#define LPI_GPIO_DS_TO_VAL(v)(v / 2 - 1)
> +#define NO_SLEW -1
> +
> +#define LPI_FUNCTION(fname) \
> + [LPI_MUX_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins,\
> + .pin = id, \
> + .slew_offset = soff,\
> + .npins = ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + LPI_MUX_gpio, \
> +
Re: [PATCH v6 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
On Wed 02 Dec 10:29 CST 2020, Srinivas Kandagatla wrote:
> Add initial pinctrl driver to support pin configuration for
> LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
> on SM8250.
>
> This IP is an additional pin control block for Audio Pins on top the
> existing SoC Top level pin-controller.
> Hardware setup looks like:
>
> TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
>
> This pin controller has some similarities compared to Top level
> msm SoC Pin controller like 'each pin belongs to a single group'
> and so on. However this one is intended to control only audio
> pins in particular, which can not be configured/touched by the
> Top level SoC pin controller except setting them as gpios.
> Apart from this, slew rate is also available in this block for
> certain pins which are connected to SLIMbus or SoundWire Bus.
>
> Signed-off-by: Srinivas Kandagatla
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> drivers/pinctrl/qcom/Kconfig | 8 +
> drivers/pinctrl/qcom/Makefile| 1 +
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 +++
> 3 files changed, 704 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 5fe7b8aaf69d..d3e4e89c2810 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -236,4 +236,12 @@ config PINCTRL_SM8250
> Qualcomm Technologies Inc TLMM block found on the Qualcomm
> Technologies Inc SM8250 platform.
>
> +config PINCTRL_LPASS_LPI
> + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
> + depends on GPIOLIB
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> + (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
> +
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 9e3d9c91a444..c8520155fb1b 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
> obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
> obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
> obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
> +obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> new file mode 100644
> index ..369ee20a7ea9
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> @@ -0,0 +1,695 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2020 Linaro Ltd.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "../core.h"
> +#include "../pinctrl-utils.h"
> +
> +#define LPI_SLEW_RATE_CTL_REG0xa000
> +#define LPI_TLMM_REG_OFFSET 0x1000
> +#define LPI_SLEW_RATE_MAX0x03
> +#define LPI_SLEW_BITS_SIZE 0x02
> +#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
> +#define LPI_GPIO_CFG_REG 0x00
> +#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
> +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
> +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
> +#define LPI_GPIO_OE_MASK BIT(9)
> +#define LPI_GPIO_VALUE_REG 0x04
> +#define LPI_GPIO_VALUE_IN_MASK BIT(0)
> +#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
> +
> +#define LPI_GPIO_BIAS_DISABLE0x0
> +#define LPI_GPIO_PULL_DOWN 0x1
> +#define LPI_GPIO_KEEPER 0x2
> +#define LPI_GPIO_PULL_UP 0x3
> +#define LPI_GPIO_DS_TO_VAL(v)(v / 2 - 1)
> +#define NO_SLEW -1
> +
> +#define LPI_FUNCTION(fname) \
> + [LPI_MUX_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins,\
> + .pin = id, \
> + .slew_offset = soff,\
> + .npins = ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + LPI_MUX_gpio, \
> + LPI_MUX_##f1, \
> +
[RESEND PATCH v6 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 +++
3 files changed, 704 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..d3e4e89c2810 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..369ee20a7ea9
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,695 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_TLMM_REG_OFFSET0x1000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_GPIO_VALUE_IN_MASK BIT(0)
+#define LPI_GPIO_VALUE_OUT_MASKBIT(1)
+
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
+#define NO_SLEW-1
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .slew_offset = soff,\
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5,\
+ }
+
+struct lpi_pingroup {
+
[PATCH v6 2/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
Add initial pinctrl driver to support pin configuration for
LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8250.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile| 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 695 +++
3 files changed, 704 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8aaf69d..d3e4e89c2810 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -236,4 +236,12 @@ config PINCTRL_SM8250
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
+config PINCTRL_LPASS_LPI
+ tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c91a444..c8520155fb1b 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
+obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
new file mode 100644
index ..369ee20a7ea9
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -0,0 +1,695 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_TLMM_REG_OFFSET0x1000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_GPIO_VALUE_IN_MASK BIT(0)
+#define LPI_GPIO_VALUE_OUT_MASKBIT(1)
+
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
+#define NO_SLEW-1
+
+#define LPI_FUNCTION(fname)\
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .pin = id, \
+ .slew_offset = soff,\
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5,\
+ }
+
+struct lpi_pingroup {
+
