Re: [PATCH v6 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

2017-08-02 Thread Jonathan Liu 
Hi Priit,

On 15 July 2017 at 00:49, Priit Laes  wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
>
> Signed-off-by: Priit Laes 
> ---
>  drivers/clk/sunxi-ng/Kconfig  |   13 +-
>  drivers/clk/sunxi-ng/Makefile |1 +-
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.c  | 1454 ++-
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.h  |   61 +-
>  include/dt-bindings/clock/sun4i-a10-ccu.h |  200 +++-
>  include/dt-bindings/clock/sun7i-a20-ccu.h |   53 +-
>  include/dt-bindings/reset/sun4i-a10-ccu.h |   69 +-
>  7 files changed, 1851 insertions(+)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h
>  create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
>  create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h



> diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c 
> b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
> new file mode 100644
> index 000..09e97d7
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c



> +static void __init sun4i_ccu_init(struct device_node *node,
> + const struct sunxi_ccu_desc *desc)
> +{
> +   void __iomem *reg;
> +   u32 val;
> +
> +   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> +   if (IS_ERR(reg)) {
> +   pr_err("%s: Could not map the clock registers\n",
> +  of_node_full_name(node));
> +   return;
> +   }
> +
> +   /* Force the PLL-Audio-1x divider to 4 */
> +   val = readl(reg + SUN4I_PLL_AUDIO_REG);

> +   val &= ~GENMASK(19, 16);
> +   writel(val | (3 << 16), reg + SUN4I_PLL_AUDIO_REG);

This doesn't work for me on A20 (440 Hz tone outputs at 880 Hz tone)
and I need to use the following instead:
   val &= ~GENMASK(29, 26);
   writel(val | (4 << 26), reg + SUN4I_PLL_AUDIO_REG);

Toggling bits 16-19 doesn't seem to have any effect on the audio for me.

Thanks.

Regards,
Jonathan

Re: [PATCH v6 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

2017-08-02 Thread Jonathan Liu 
Hi Priit,

On 15 July 2017 at 00:49, Priit Laes  wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
>
> Signed-off-by: Priit Laes 
> ---
>  drivers/clk/sunxi-ng/Kconfig  |   13 +-
>  drivers/clk/sunxi-ng/Makefile |1 +-
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.c  | 1454 ++-
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.h  |   61 +-
>  include/dt-bindings/clock/sun4i-a10-ccu.h |  200 +++-
>  include/dt-bindings/clock/sun7i-a20-ccu.h |   53 +-
>  include/dt-bindings/reset/sun4i-a10-ccu.h |   69 +-
>  7 files changed, 1851 insertions(+)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h
>  create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
>  create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h



> diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c 
> b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
> new file mode 100644
> index 000..09e97d7
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c



> +static void __init sun4i_ccu_init(struct device_node *node,
> + const struct sunxi_ccu_desc *desc)
> +{
> +   void __iomem *reg;
> +   u32 val;
> +
> +   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> +   if (IS_ERR(reg)) {
> +   pr_err("%s: Could not map the clock registers\n",
> +  of_node_full_name(node));
> +   return;
> +   }
> +
> +   /* Force the PLL-Audio-1x divider to 4 */
> +   val = readl(reg + SUN4I_PLL_AUDIO_REG);

> +   val &= ~GENMASK(19, 16);
> +   writel(val | (3 << 16), reg + SUN4I_PLL_AUDIO_REG);

This doesn't work for me on A20 (440 Hz tone outputs at 880 Hz tone)
and I need to use the following instead:
   val &= ~GENMASK(29, 26);
   writel(val | (4 << 26), reg + SUN4I_PLL_AUDIO_REG);

Toggling bits 16-19 doesn't seem to have any effect on the audio for me.

Thanks.

Regards,
Jonathan

Re: [PATCH v6 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

2017-07-17 Thread Maxime Ripard 
Hi,

On Fri, Jul 14, 2017 at 05:49:24PM +0300, Priit Laes wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
> 
> Signed-off-by: Priit Laes 
> ---
>  drivers/clk/sunxi-ng/Kconfig  |   13 +-
>  drivers/clk/sunxi-ng/Makefile |1 +-
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.c  | 1454 ++-
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.h  |   61 +-
>  include/dt-bindings/clock/sun4i-a10-ccu.h |  200 +++-
>  include/dt-bindings/clock/sun7i-a20-ccu.h |   53 +-
>  include/dt-bindings/reset/sun4i-a10-ccu.h |   69 +-
>  7 files changed, 1851 insertions(+)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h
>  create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
>  create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h
> 
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 7342928..1b5cea9 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -11,6 +11,19 @@ config SUN50I_A64_CCU
>   default ARM64 && ARCH_SUNXI
>   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>  
> +config SUNXI_A10_CCU
> + bool "Support for the Allwinner A10/A20 CCU"
> + select SUNXI_CCU_DIV
> + select SUNXI_CCU_MULT
> + select SUNXI_CCU_NK
> + select SUNXI_CCU_NKM
> + select SUNXI_CCU_NM
> + select SUNXI_CCU_MP
> + select SUNXI_CCU_PHASE
> + default MACH_SUN4I
> + default MACH_SUN7I
> + depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST

I'm a bit late on this one, but I agree with Olliver, it should be
called SUN4I_A10. This is what we do for all the other symbols (and it
should be ordered as such).

> +
>  config SUN5I_CCU
>   bool "Support for the Allwinner sun5i family CCM"
>   default MACH_SUN5I
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 0c45fa5..01e958c 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -21,6 +21,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o
>  obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
>  obj-$(CONFIG_SUN5I_CCU)  += ccu-sun5i.o
>  obj-$(CONFIG_SUN6I_A31_CCU)  += ccu-sun6i-a31.o
> +obj-$(CONFIG_SUNXI_A10_CCU)  += ccu-sun4i-a10.o

The ordering is wrong here too.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH v6 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

2017-07-17 Thread Maxime Ripard 
Hi,

On Fri, Jul 14, 2017 at 05:49:24PM +0300, Priit Laes wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
> 
> Signed-off-by: Priit Laes 
> ---
>  drivers/clk/sunxi-ng/Kconfig  |   13 +-
>  drivers/clk/sunxi-ng/Makefile |1 +-
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.c  | 1454 ++-
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.h  |   61 +-
>  include/dt-bindings/clock/sun4i-a10-ccu.h |  200 +++-
>  include/dt-bindings/clock/sun7i-a20-ccu.h |   53 +-
>  include/dt-bindings/reset/sun4i-a10-ccu.h |   69 +-
>  7 files changed, 1851 insertions(+)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h
>  create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
>  create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h
> 
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 7342928..1b5cea9 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -11,6 +11,19 @@ config SUN50I_A64_CCU
>   default ARM64 && ARCH_SUNXI
>   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>  
> +config SUNXI_A10_CCU
> + bool "Support for the Allwinner A10/A20 CCU"
> + select SUNXI_CCU_DIV
> + select SUNXI_CCU_MULT
> + select SUNXI_CCU_NK
> + select SUNXI_CCU_NKM
> + select SUNXI_CCU_NM
> + select SUNXI_CCU_MP
> + select SUNXI_CCU_PHASE
> + default MACH_SUN4I
> + default MACH_SUN7I
> + depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST

I'm a bit late on this one, but I agree with Olliver, it should be
called SUN4I_A10. This is what we do for all the other symbols (and it
should be ordered as such).

> +
>  config SUN5I_CCU
>   bool "Support for the Allwinner sun5i family CCM"
>   default MACH_SUN5I
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 0c45fa5..01e958c 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -21,6 +21,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o
>  obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
>  obj-$(CONFIG_SUN5I_CCU)  += ccu-sun5i.o
>  obj-$(CONFIG_SUN6I_A31_CCU)  += ccu-sun6i-a31.o
> +obj-$(CONFIG_SUNXI_A10_CCU)  += ccu-sun4i-a10.o

The ordering is wrong here too.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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[PATCH v6 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

2017-07-14 Thread Priit Laes 
Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.

Signed-off-by: Priit Laes 
---
 drivers/clk/sunxi-ng/Kconfig  |   13 +-
 drivers/clk/sunxi-ng/Makefile |1 +-
 drivers/clk/sunxi-ng/ccu-sun4i-a10.c  | 1454 ++-
 drivers/clk/sunxi-ng/ccu-sun4i-a10.h  |   61 +-
 include/dt-bindings/clock/sun4i-a10-ccu.h |  200 +++-
 include/dt-bindings/clock/sun7i-a20-ccu.h |   53 +-
 include/dt-bindings/reset/sun4i-a10-ccu.h |   69 +-
 7 files changed, 1851 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h
 create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
 create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
 create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 7342928..1b5cea9 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -11,6 +11,19 @@ config SUN50I_A64_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
+config SUNXI_A10_CCU
+   bool "Support for the Allwinner A10/A20 CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_MULT
+   select SUNXI_CCU_NK
+   select SUNXI_CCU_NKM
+   select SUNXI_CCU_NM
+   select SUNXI_CCU_MP
+   select SUNXI_CCU_PHASE
+   default MACH_SUN4I
+   default MACH_SUN7I
+   depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
+
 config SUN5I_CCU
bool "Support for the Allwinner sun5i family CCM"
default MACH_SUN5I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 0c45fa5..01e958c 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -21,6 +21,7 @@ lib-$(CONFIG_SUNXI_CCU)   += ccu_mp.o
 obj-$(CONFIG_SUN50I_A64_CCU)   += ccu-sun50i-a64.o
 obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
 obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
+obj-$(CONFIG_SUNXI_A10_CCU)+= ccu-sun4i-a10.o
 obj-$(CONFIG_SUN8I_A23_CCU)+= ccu-sun8i-a23.o
 obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o
 obj-$(CONFIG_SUN8I_A83T_CCU)   += ccu-sun8i-a83t.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c 
b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
new file mode 100644
index 000..09e97d7
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -0,0 +1,1454 @@
+/*
+ * Copyright (c) 2017 Priit Laes .
+ * Copyright (c) 2017 Maxime Ripard.
+ * Copyright (c) 2017 Jonathan Liu.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun4i-a10.h"
+
+static struct ccu_nkmp pll_core_clk = {
+   .enable = BIT(31),
+   .n  = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+   .k  = _SUNXI_CCU_MULT(4, 2),
+   .m  = _SUNXI_CCU_DIV(0, 2),
+   .p  = _SUNXI_CCU_DIV(16, 2),
+   .common = {
+   .reg= 0x000,
+   .hw.init= CLK_HW_INIT("pll-core",
+ "hosc",
+ _nkmp_ops,
+ 0),
+   },
+};
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names.
+ */
+#define SUN4I_PLL_AUDIO_REG0x008
+static struct ccu_nm pll_audio_base_clk = {
+   .enable = BIT(31),
+   .n  = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
+   .m  = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
+   .common = {
+   .reg= 0x008,
+   .hw.init= CLK_HW_INIT("pll-audio-base",
+ "hosc",
+ _nm_ops,
+ 0),
+   },
+
+};
+
+static struct ccu_mult pll_video0_clk = {
+   .enable = BIT(31),
+   .mult   = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
+   .frac   =

[PATCH v6 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

2017-07-14 Thread Priit Laes 
Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.

Signed-off-by: Priit Laes 
---
 drivers/clk/sunxi-ng/Kconfig  |   13 +-
 drivers/clk/sunxi-ng/Makefile |1 +-
 drivers/clk/sunxi-ng/ccu-sun4i-a10.c  | 1454 ++-
 drivers/clk/sunxi-ng/ccu-sun4i-a10.h  |   61 +-
 include/dt-bindings/clock/sun4i-a10-ccu.h |  200 +++-
 include/dt-bindings/clock/sun7i-a20-ccu.h |   53 +-
 include/dt-bindings/reset/sun4i-a10-ccu.h |   69 +-
 7 files changed, 1851 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h
 create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
 create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
 create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 7342928..1b5cea9 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -11,6 +11,19 @@ config SUN50I_A64_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
+config SUNXI_A10_CCU
+   bool "Support for the Allwinner A10/A20 CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_MULT
+   select SUNXI_CCU_NK
+   select SUNXI_CCU_NKM
+   select SUNXI_CCU_NM
+   select SUNXI_CCU_MP
+   select SUNXI_CCU_PHASE
+   default MACH_SUN4I
+   default MACH_SUN7I
+   depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
+
 config SUN5I_CCU
bool "Support for the Allwinner sun5i family CCM"
default MACH_SUN5I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 0c45fa5..01e958c 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -21,6 +21,7 @@ lib-$(CONFIG_SUNXI_CCU)   += ccu_mp.o
 obj-$(CONFIG_SUN50I_A64_CCU)   += ccu-sun50i-a64.o
 obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
 obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
+obj-$(CONFIG_SUNXI_A10_CCU)+= ccu-sun4i-a10.o
 obj-$(CONFIG_SUN8I_A23_CCU)+= ccu-sun8i-a23.o
 obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o
 obj-$(CONFIG_SUN8I_A83T_CCU)   += ccu-sun8i-a83t.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c 
b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
new file mode 100644
index 000..09e97d7
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -0,0 +1,1454 @@
+/*
+ * Copyright (c) 2017 Priit Laes .
+ * Copyright (c) 2017 Maxime Ripard.
+ * Copyright (c) 2017 Jonathan Liu.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun4i-a10.h"
+
+static struct ccu_nkmp pll_core_clk = {
+   .enable = BIT(31),
+   .n  = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+   .k  = _SUNXI_CCU_MULT(4, 2),
+   .m  = _SUNXI_CCU_DIV(0, 2),
+   .p  = _SUNXI_CCU_DIV(16, 2),
+   .common = {
+   .reg= 0x000,
+   .hw.init= CLK_HW_INIT("pll-core",
+ "hosc",
+ _nkmp_ops,
+ 0),
+   },
+};
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names.
+ */
+#define SUN4I_PLL_AUDIO_REG0x008
+static struct ccu_nm pll_audio_base_clk = {
+   .enable = BIT(31),
+   .n  = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
+   .m  = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
+   .common = {
+   .reg= 0x008,
+   .hw.init= CLK_HW_INIT("pll-audio-base",
+ "hosc",
+ _nm_ops,
+ 0),
+   },
+
+};
+
+static struct ccu_mult pll_video0_clk = {
+   .enable = BIT(31),
+   .mult   = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
+   .frac   = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
+