[PATCH v6 5/6] g_NCR5380: Re-work PDMA loops

[Finn Thain]

From: Ondrej Zary 

The polling loops in pread() and pwrite() can easily become infinite
loops and hang the machine.

Merge the IRQ check into host buffer wait loop and add polling limit.

Also place a limit on polling for 53C80 registers accessibility.

[Use NCR5380_poll_politely2() for register polling. Rely on polling for
gated IRQ rather than polling for phase error, like the algorithm in the
53c400 datasheet. Move DTC436 workarounds into a separate patch.
Factor-out common code as wait_for_53c80_access(). Rework the residual
correction. -- F.T.]

Signed-off-by: Ondrej Zary 
Signed-off-by: Finn Thain 
---
 drivers/scsi/g_NCR5380.c | 173 +--
 1 file changed, 92 insertions(+), 81 deletions(-)

diff --git a/drivers/scsi/g_NCR5380.c b/drivers/scsi/g_NCR5380.c
index 33e1a480c903..137ec58c43ac 100644
--- a/drivers/scsi/g_NCR5380.c
+++ b/drivers/scsi/g_NCR5380.c
@@ -480,6 +480,28 @@ static void generic_NCR5380_release_resources(struct 
Scsi_Host *instance)
release_mem_region(base, region_size);
 }
 
+/* wait_for_53c80_access - wait for 53C80 registers to become accessible
+ * @hostdata: scsi host private data
+ *
+ * The registers within the 53C80 logic block are inaccessible until
+ * bit 7 in the 53C400 control status register gets asserted.
+ */
+
+static void wait_for_53c80_access(struct NCR5380_hostdata *hostdata)
+{
+   int count = 1;
+
+   do {
+   if (NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)
+   return;
+   } while (--count > 0);
+
+   scmd_printk(KERN_ERR, hostdata->connected,
+   "53c80 registers not accessible, device will be reset\n");
+   NCR5380_write(hostdata->c400_ctl_status, CSR_RESET);
+   NCR5380_write(hostdata->c400_ctl_status, CSR_BASE);
+}
+
 /**
  * generic_NCR5380_precv - pseudo DMA receive
  * @hostdata: scsi host private data
@@ -492,18 +514,23 @@ static void generic_NCR5380_release_resources(struct 
Scsi_Host *instance)
 static inline int generic_NCR5380_precv(struct NCR5380_hostdata *hostdata,
 unsigned char *dst, int len)
 {
-   int blocks = len / 128;
+   int residual;
int start = 0;
 
NCR5380_write(hostdata->c400_ctl_status, CSR_BASE | CSR_TRANS_DIR);
-   NCR5380_write(hostdata->c400_blk_cnt, blocks);
-   while (1) {
-   if (NCR5380_read(hostdata->c400_blk_cnt) == 0)
+   NCR5380_write(hostdata->c400_blk_cnt, len / 128);
+
+   do {
+   if (NCR5380_poll_politely2(hostdata, hostdata->c400_ctl_status,
+  CSR_HOST_BUF_NOT_RDY, 0,
+  hostdata->c400_ctl_status,
+  CSR_GATED_53C80_IRQ,
+  CSR_GATED_53C80_IRQ, HZ / 64) < 0)
+   break;
+
+   if (NCR5380_read(hostdata->c400_ctl_status) &
+   CSR_HOST_BUF_NOT_RDY)
break;
-   if (NCR5380_read(hostdata->c400_ctl_status) & 
CSR_GATED_53C80_IRQ)
-   goto out_wait;
-   while (NCR5380_read(hostdata->c400_ctl_status) & 
CSR_HOST_BUF_NOT_RDY)
-   ; /* FIXME - no timeout */
 
if (hostdata->io_port && hostdata->io_width == 2)
insw(hostdata->io_port + hostdata->c400_host_buf,
@@ -514,44 +541,26 @@ static inline int generic_NCR5380_precv(struct 
NCR5380_hostdata *hostdata,
else
memcpy_fromio(dst + start,
hostdata->io + NCR53C400_host_buffer, 128);
-
start += 128;
-   blocks--;
-   }
-
-   if (blocks) {
-   while (NCR5380_read(hostdata->c400_ctl_status) & 
CSR_HOST_BUF_NOT_RDY)
-   ; /* FIXME - no timeout */
+   } while (start < len);
 
-   if (hostdata->io_port && hostdata->io_width == 2)
-   insw(hostdata->io_port + hostdata->c400_host_buf,
-   dst + start, 64);
-   else if (hostdata->io_port)
-   insb(hostdata->io_port + hostdata->c400_host_buf,
-   dst + start, 128);
-   else
-   memcpy_fromio(dst + start,
-   hostdata->io + NCR53C400_host_buffer, 128);
+   residual = len - start;
 
-   start += 128;
-   blocks--;
+   if (residual != 0) {
+   /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */
+   NCR5380_write(hostdata->c400_ctl_status, CSR_RESET);
+   NCR5380_write(hostdata->c400_ctl_status, CSR_BASE);
}
+   

[PATCH v6 5/6] g_NCR5380: Re-work PDMA loops

[Finn Thain]

From: Ondrej Zary 

The polling loops in pread() and pwrite() can easily become infinite
loops and hang the machine.

Merge the IRQ check into host buffer wait loop and add polling limit.

Also place a limit on polling for 53C80 registers accessibility.

[Use NCR5380_poll_politely2() for register polling. Rely on polling for
gated IRQ rather than polling for phase error, like the algorithm in the
53c400 datasheet. Move DTC436 workarounds into a separate patch.
Factor-out common code as wait_for_53c80_access(). Rework the residual
correction. -- F.T.]

Signed-off-by: Ondrej Zary 
Signed-off-by: Finn Thain 
---
 drivers/scsi/g_NCR5380.c | 173 +--
 1 file changed, 92 insertions(+), 81 deletions(-)

diff --git a/drivers/scsi/g_NCR5380.c b/drivers/scsi/g_NCR5380.c
index 33e1a480c903..137ec58c43ac 100644
--- a/drivers/scsi/g_NCR5380.c
+++ b/drivers/scsi/g_NCR5380.c
@@ -480,6 +480,28 @@ static void generic_NCR5380_release_resources(struct 
Scsi_Host *instance)
release_mem_region(base, region_size);
 }
 
+/* wait_for_53c80_access - wait for 53C80 registers to become accessible
+ * @hostdata: scsi host private data
+ *
+ * The registers within the 53C80 logic block are inaccessible until
+ * bit 7 in the 53C400 control status register gets asserted.
+ */
+
+static void wait_for_53c80_access(struct NCR5380_hostdata *hostdata)
+{
+   int count = 1;
+
+   do {
+   if (NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)
+   return;
+   } while (--count > 0);
+
+   scmd_printk(KERN_ERR, hostdata->connected,
+   "53c80 registers not accessible, device will be reset\n");
+   NCR5380_write(hostdata->c400_ctl_status, CSR_RESET);
+   NCR5380_write(hostdata->c400_ctl_status, CSR_BASE);
+}
+
 /**
  * generic_NCR5380_precv - pseudo DMA receive
  * @hostdata: scsi host private data
@@ -492,18 +514,23 @@ static void generic_NCR5380_release_resources(struct 
Scsi_Host *instance)
 static inline int generic_NCR5380_precv(struct NCR5380_hostdata *hostdata,
 unsigned char *dst, int len)
 {
-   int blocks = len / 128;
+   int residual;
int start = 0;
 
NCR5380_write(hostdata->c400_ctl_status, CSR_BASE | CSR_TRANS_DIR);
-   NCR5380_write(hostdata->c400_blk_cnt, blocks);
-   while (1) {
-   if (NCR5380_read(hostdata->c400_blk_cnt) == 0)
+   NCR5380_write(hostdata->c400_blk_cnt, len / 128);
+
+   do {
+   if (NCR5380_poll_politely2(hostdata, hostdata->c400_ctl_status,
+  CSR_HOST_BUF_NOT_RDY, 0,
+  hostdata->c400_ctl_status,
+  CSR_GATED_53C80_IRQ,
+  CSR_GATED_53C80_IRQ, HZ / 64) < 0)
+   break;
+
+   if (NCR5380_read(hostdata->c400_ctl_status) &
+   CSR_HOST_BUF_NOT_RDY)
break;
-   if (NCR5380_read(hostdata->c400_ctl_status) & 
CSR_GATED_53C80_IRQ)
-   goto out_wait;
-   while (NCR5380_read(hostdata->c400_ctl_status) & 
CSR_HOST_BUF_NOT_RDY)
-   ; /* FIXME - no timeout */
 
if (hostdata->io_port && hostdata->io_width == 2)
insw(hostdata->io_port + hostdata->c400_host_buf,
@@ -514,44 +541,26 @@ static inline int generic_NCR5380_precv(struct 
NCR5380_hostdata *hostdata,
else
memcpy_fromio(dst + start,
hostdata->io + NCR53C400_host_buffer, 128);
-
start += 128;
-   blocks--;
-   }
-
-   if (blocks) {
-   while (NCR5380_read(hostdata->c400_ctl_status) & 
CSR_HOST_BUF_NOT_RDY)
-   ; /* FIXME - no timeout */
+   } while (start < len);
 
-   if (hostdata->io_port && hostdata->io_width == 2)
-   insw(hostdata->io_port + hostdata->c400_host_buf,
-   dst + start, 64);
-   else if (hostdata->io_port)
-   insb(hostdata->io_port + hostdata->c400_host_buf,
-   dst + start, 128);
-   else
-   memcpy_fromio(dst + start,
-   hostdata->io + NCR53C400_host_buffer, 128);
+   residual = len - start;
 
-   start += 128;
-   blocks--;
+   if (residual != 0) {
+   /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */
+   NCR5380_write(hostdata->c400_ctl_status, CSR_RESET);
+   NCR5380_write(hostdata->c400_ctl_status, CSR_BASE);
}
+   wait_for_53c80_access(hostdata);
 
-   if (!(NCR5380_read(hostdata->c400_ctl_status) &