Re: [PATCH v7 2/3] clk: clk-pic32: Add PIC32 clock driver

2016-02-19 Thread Purna Chandra Mandal 
On 02/20/2016 01:46 AM, Michael Turquette wrote:

> Quoting Joshua Henderson (2016-02-19 08:25:35)
>> +const struct clk_ops pic32_roclk_ops = {
>> +   .enable = roclk_enable,
>> +   .disable= roclk_disable,
>> +   .is_enabled = roclk_is_enabled,
>> +   .get_parent = roclk_get_parent,
>> +   .set_parent = roclk_set_parent,
>> +   .determine_rate = roclk_determine_rate,
>> +   .recalc_rate= roclk_recalc_rate,
>> +   .round_rate = roclk_round_rate,
>> +   .set_rate_and_parent= roclk_set_rate_and_parent,
>> +   .set_rate   = roclk_set_rate,
>> +   .init   = roclk_init,
>> +};
> You can remove .round_rate and only use .determine_rate.

Ack. Will remove .round_rate.

> ...
>> +CLK_OF_DECLARE(pic32mzda_clk, "microchip,pic32mzda-clk", 
>> pic32mzda_clock_init);
> Can you make this a platform_driver instead of using CLK_OF_DECLARE? I
> asked this in v6 but there was no response.

Mike,
I tried to use platform_driver approach, but didn't work for me.
On MIPS/PIC32 first call of clk_get() happens from "start_kernel -> 
time_init()->
plat_time_init()" which is very early in boot sequence even before execution of
early_initcall(). In short, by platform_driver way I'was not able to register 
clock(s)
before the first clock user becomes ready. Whereas with CLK_OF_DECLARE() I can
explicitly call of_clk_init() in plat_time_init() just before calling clk_get().

Please suggest me if you have any reference to avoid my case.

> Regards,
> Mike
>
>> -- 
>> 1.7.9.5
>>

Re: [PATCH v7 2/3] clk: clk-pic32: Add PIC32 clock driver

2016-02-19 Thread Purna Chandra Mandal 
On 02/20/2016 01:46 AM, Michael Turquette wrote:

> Quoting Joshua Henderson (2016-02-19 08:25:35)
>> +const struct clk_ops pic32_roclk_ops = {
>> +   .enable = roclk_enable,
>> +   .disable= roclk_disable,
>> +   .is_enabled = roclk_is_enabled,
>> +   .get_parent = roclk_get_parent,
>> +   .set_parent = roclk_set_parent,
>> +   .determine_rate = roclk_determine_rate,
>> +   .recalc_rate= roclk_recalc_rate,
>> +   .round_rate = roclk_round_rate,
>> +   .set_rate_and_parent= roclk_set_rate_and_parent,
>> +   .set_rate   = roclk_set_rate,
>> +   .init   = roclk_init,
>> +};
> You can remove .round_rate and only use .determine_rate.

Ack. Will remove .round_rate.

> ...
>> +CLK_OF_DECLARE(pic32mzda_clk, "microchip,pic32mzda-clk", 
>> pic32mzda_clock_init);
> Can you make this a platform_driver instead of using CLK_OF_DECLARE? I
> asked this in v6 but there was no response.

Mike,
I tried to use platform_driver approach, but didn't work for me.
On MIPS/PIC32 first call of clk_get() happens from "start_kernel -> 
time_init()->
plat_time_init()" which is very early in boot sequence even before execution of
early_initcall(). In short, by platform_driver way I'was not able to register 
clock(s)
before the first clock user becomes ready. Whereas with CLK_OF_DECLARE() I can
explicitly call of_clk_init() in plat_time_init() just before calling clk_get().

Please suggest me if you have any reference to avoid my case.

> Regards,
> Mike
>
>> -- 
>> 1.7.9.5
>>

Re: [PATCH v7 2/3] clk: clk-pic32: Add PIC32 clock driver

2016-02-19 Thread Michael Turquette 
Quoting Joshua Henderson (2016-02-19 08:25:35)
> +const struct clk_ops pic32_roclk_ops = {
> +   .enable = roclk_enable,
> +   .disable= roclk_disable,
> +   .is_enabled = roclk_is_enabled,
> +   .get_parent = roclk_get_parent,
> +   .set_parent = roclk_set_parent,
> +   .determine_rate = roclk_determine_rate,
> +   .recalc_rate= roclk_recalc_rate,
> +   .round_rate = roclk_round_rate,
> +   .set_rate_and_parent= roclk_set_rate_and_parent,
> +   .set_rate   = roclk_set_rate,
> +   .init   = roclk_init,
> +};

You can remove .round_rate and only use .determine_rate.

...
> +CLK_OF_DECLARE(pic32mzda_clk, "microchip,pic32mzda-clk", 
> pic32mzda_clock_init);

Can you make this a platform_driver instead of using CLK_OF_DECLARE? I
asked this in v6 but there was no response.

Regards,
Mike

> -- 
> 1.7.9.5
>

Re: [PATCH v7 2/3] clk: clk-pic32: Add PIC32 clock driver

2016-02-19 Thread Michael Turquette 
Quoting Joshua Henderson (2016-02-19 08:25:35)
> +const struct clk_ops pic32_roclk_ops = {
> +   .enable = roclk_enable,
> +   .disable= roclk_disable,
> +   .is_enabled = roclk_is_enabled,
> +   .get_parent = roclk_get_parent,
> +   .set_parent = roclk_set_parent,
> +   .determine_rate = roclk_determine_rate,
> +   .recalc_rate= roclk_recalc_rate,
> +   .round_rate = roclk_round_rate,
> +   .set_rate_and_parent= roclk_set_rate_and_parent,
> +   .set_rate   = roclk_set_rate,
> +   .init   = roclk_init,
> +};

You can remove .round_rate and only use .determine_rate.

...
> +CLK_OF_DECLARE(pic32mzda_clk, "microchip,pic32mzda-clk", 
> pic32mzda_clock_init);

Can you make this a platform_driver instead of using CLK_OF_DECLARE? I
asked this in v6 but there was no response.

Regards,
Mike

> -- 
> 1.7.9.5
>

[PATCH v7 2/3] clk: clk-pic32: Add PIC32 clock driver

2016-02-19 Thread Joshua Henderson 
From: Purna Chandra Mandal 

This clock driver implements PIC32 specific clock-tree. clock-tree
entities can only be configured through device-tree file (OF).

Signed-off-by: Purna Chandra Mandal 
Signed-off-by: Joshua Henderson 
Cc: Ralf Baechle 
Cc: Michael Turquette 
Cc: Stephen Boyd 
---
Note: Please pull this complete series through the MIPS tree.

Changes since v6:
- Reworked PIC32 clock driver based on review.
- PIC32 clock driver now separate core functionality from platform
  specific clock-submodule binding/hierarchy.
- moved PIC32 driver under clk/microchip/
- core clk functionality now in clk/microchip/clk-core.c
- driver now doesn't use device-tree for clock submodules.
- platform now statically defines clock submodule data-structures
  and bind them accordingly.
Changes since v5:
- sort linux includes and asm includes.
- use BIT() wherever applicable
- drop 'microchip,ignore-unused' usage, handling in favor of critical
  clock
- drop 'fixed divider' handling for periph clock
- drop use of 'debug_init()' clk operation callback for register dump
- drop clk_lock(), clk_unlock() spinlock wrapper
- drop unimplemented pic32_devcon_syslock() macro
- use readl()/writel() instead of clk_readl()/clk_writel()
- drop redundant spinlock, unlock calls in sosc_clk_enable()/disable()
- use CLK_SET_RATE_GATE, _SET_PARENT_GATE for refo-clocks
- use kcalloc() instead of kmalloc() wherever applicable
- use of_io_request_and_map() in soc_clock_init()
- drop use of pbclk(/roclk)_endisable() inline function
- use readl_poll_timeout_atomic() for wait_for_bit() type loop
- drop cpu_relax() after clk gating
- promote u8, u16 to u32 wherever applicable
- fix sosc clock status polling
- drop memory alloc from pic32_of_clk_get_parent_indices() instead
  callers  will supply buffer to hold output parent indices
- reword comments about spll_clk_set_rate() pre-conditions
- drop use of CLK_BASIC wherever applicable
- reword comments in sclk_set_parent()
Changes since v4: None
Changes since v3: None
Changes since v2:
- Replace __clk_debug with pr_debug
- Add of_clk_parent_fill usage in PIC32 clock driver
Changes since v1:
- Remove unused PIC32 MPLL support.
- Remove support for initializing default parent/rate for REFOSC
  clocks.
---
 drivers/clk/Kconfig   |3 +
 drivers/clk/Makefile  |1 +
 drivers/clk/microchip/Makefile|2 +
 drivers/clk/microchip/clk-core.c  |  955 +
 drivers/clk/microchip/clk-core.h  |   78 +++
 drivers/clk/microchip/clk-pic32mzda.c |  214 
 6 files changed, 1253 insertions(+)
 create mode 100644 drivers/clk/microchip/Makefile
 create mode 100644 drivers/clk/microchip/clk-core.c
 create mode 100644 drivers/clk/microchip/clk-core.h
 create mode 100644 drivers/clk/microchip/clk-pic32mzda.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index eca8e01..41e9c14 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -200,6 +200,9 @@ config COMMON_CLK_CDCE706
---help---
  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
 
+config COMMON_CLK_PIC32
+   def_bool COMMON_CLK && MACH_PIC32
+
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/qcom/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b038e36..66a6a6b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_ARCH_MXC)+= imx/
 obj-$(CONFIG_MACH_INGENIC) += ingenic/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
+obj-$(CONFIG_MACH_PIC32)   += microchip/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP) += mmp/
 endif
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 000..2152f41
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o
+obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o
diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c
new file mode 100644
index 000..fd12db8
--- /dev/null
+++ b/drivers/clk/microchip/clk-core.c
@@ -0,0 +1,955 @@
+/*
+ * Purna Chandra Mandal,
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version

[PATCH v7 2/3] clk: clk-pic32: Add PIC32 clock driver

2016-02-19 Thread Joshua Henderson 
From: Purna Chandra Mandal 

This clock driver implements PIC32 specific clock-tree. clock-tree
entities can only be configured through device-tree file (OF).

Signed-off-by: Purna Chandra Mandal 
Signed-off-by: Joshua Henderson 
Cc: Ralf Baechle 
Cc: Michael Turquette 
Cc: Stephen Boyd 
---
Note: Please pull this complete series through the MIPS tree.

Changes since v6:
- Reworked PIC32 clock driver based on review.
- PIC32 clock driver now separate core functionality from platform
  specific clock-submodule binding/hierarchy.
- moved PIC32 driver under clk/microchip/
- core clk functionality now in clk/microchip/clk-core.c
- driver now doesn't use device-tree for clock submodules.
- platform now statically defines clock submodule data-structures
  and bind them accordingly.
Changes since v5:
- sort linux includes and asm includes.
- use BIT() wherever applicable
- drop 'microchip,ignore-unused' usage, handling in favor of critical
  clock
- drop 'fixed divider' handling for periph clock
- drop use of 'debug_init()' clk operation callback for register dump
- drop clk_lock(), clk_unlock() spinlock wrapper
- drop unimplemented pic32_devcon_syslock() macro
- use readl()/writel() instead of clk_readl()/clk_writel()
- drop redundant spinlock, unlock calls in sosc_clk_enable()/disable()
- use CLK_SET_RATE_GATE, _SET_PARENT_GATE for refo-clocks
- use kcalloc() instead of kmalloc() wherever applicable
- use of_io_request_and_map() in soc_clock_init()
- drop use of pbclk(/roclk)_endisable() inline function
- use readl_poll_timeout_atomic() for wait_for_bit() type loop
- drop cpu_relax() after clk gating
- promote u8, u16 to u32 wherever applicable
- fix sosc clock status polling
- drop memory alloc from pic32_of_clk_get_parent_indices() instead
  callers  will supply buffer to hold output parent indices
- reword comments about spll_clk_set_rate() pre-conditions
- drop use of CLK_BASIC wherever applicable
- reword comments in sclk_set_parent()
Changes since v4: None
Changes since v3: None
Changes since v2:
- Replace __clk_debug with pr_debug
- Add of_clk_parent_fill usage in PIC32 clock driver
Changes since v1:
- Remove unused PIC32 MPLL support.
- Remove support for initializing default parent/rate for REFOSC
  clocks.
---
 drivers/clk/Kconfig   |3 +
 drivers/clk/Makefile  |1 +
 drivers/clk/microchip/Makefile|2 +
 drivers/clk/microchip/clk-core.c  |  955 +
 drivers/clk/microchip/clk-core.h  |   78 +++
 drivers/clk/microchip/clk-pic32mzda.c |  214 
 6 files changed, 1253 insertions(+)
 create mode 100644 drivers/clk/microchip/Makefile
 create mode 100644 drivers/clk/microchip/clk-core.c
 create mode 100644 drivers/clk/microchip/clk-core.h
 create mode 100644 drivers/clk/microchip/clk-pic32mzda.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index eca8e01..41e9c14 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -200,6 +200,9 @@ config COMMON_CLK_CDCE706
---help---
  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
 
+config COMMON_CLK_PIC32
+   def_bool COMMON_CLK && MACH_PIC32
+
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/qcom/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b038e36..66a6a6b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_ARCH_MXC)+= imx/
 obj-$(CONFIG_MACH_INGENIC) += ingenic/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
+obj-$(CONFIG_MACH_PIC32)   += microchip/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_ARCH_MMP) += mmp/
 endif
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 000..2152f41
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o
+obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o
diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c
new file mode 100644
index 000..fd12db8
--- /dev/null
+++ b/drivers/clk/microchip/clk-core.c
@@ -0,0 +1,955 @@
+/*
+ * Purna Chandra Mandal,
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty