Re: [PATCH v7 4/8] dt-bindings: Add a binding for Mediatek Video Encoder

2016-04-22 Thread kbuild test robot
Hi,

[auto build test ERROR on linuxtv-media/master]
[also build test ERROR on v4.6-rc4 next-20160421]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improving the system]

url:
https://github.com/0day-ci/linux/commits/Tiffany-Lin/Add-MT8173-Video-Encoder-Driver-and-VPU-Driver/20160422-123111
base:   git://linuxtv.org/media_tree.git master
config: i386-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

>> ERROR: "max_pfn" [drivers/media/platform/mtk-vpu/mtk-vpu.ko] undefined!

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data


Re: [PATCH v7 4/8] dt-bindings: Add a binding for Mediatek Video Encoder

2016-04-22 Thread kbuild test robot
Hi,

[auto build test ERROR on linuxtv-media/master]
[also build test ERROR on v4.6-rc4 next-20160421]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improving the system]

url:
https://github.com/0day-ci/linux/commits/Tiffany-Lin/Add-MT8173-Video-Encoder-Driver-and-VPU-Driver/20160422-123111
base:   git://linuxtv.org/media_tree.git master
config: i386-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

>> ERROR: "max_pfn" [drivers/media/platform/mtk-vpu/mtk-vpu.ko] undefined!

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data


[PATCH v7 4/8] dt-bindings: Add a binding for Mediatek Video Encoder

2016-04-21 Thread Tiffany Lin
Add a DT binding documentation of Video Encoder for the
MT8173 SoC from Mediatek.

Signed-off-by: Tiffany Lin 
Acked-by: Rob Herring 

---
 .../devicetree/bindings/media/mediatek-vcodec.txt  |   59 
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec.txt

diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt 
b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
new file mode 100644
index 000..59a47a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
@@ -0,0 +1,59 @@
+Mediatek Video Codec
+
+Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
+supports high resolution encoding functionalities.
+
+Required properties:
+- compatible : "mediatek,mt8173-vcodec-enc" for encoder
+- reg : Physical base address of the video codec registers and length of
+  memory mapped region.
+- interrupts : interrupt number to the cpu.
+- mediatek,larb : must contain the local arbiters in the current Socs.
+- clocks : list of clock specifiers, corresponding to entries in
+  the clock-names property.
+- clock-names: encoder must contain "venc_sel_src", "venc_sel",
+- "venc_lt_sel_src", "venc_lt_sel".
+- iommus : should point to the respective IOMMU block with master port as
+  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+  for details.
+- mediatek,vpu : the node of video processor unit
+
+Example:
+vcodec_enc: vcodec@0x18002000 {
+compatible = "mediatek,mt8173-vcodec-enc";
+reg = <0 0x18002000 0 0x1000>,/*VENC_SYS*/
+  <0 0x19002000 0 0x1000>;/*VENC_LT_SYS*/
+interrupts = ,
+;
+mediatek,larb = <>,
+   <>;
+iommus = < M4U_PORT_VENC_RCPU>,
+ < M4U_PORT_VENC_REC>,
+ < M4U_PORT_VENC_BSDMA>,
+ < M4U_PORT_VENC_SV_COMV>,
+ < M4U_PORT_VENC_RD_COMV>,
+ < M4U_PORT_VENC_CUR_LUMA>,
+ < M4U_PORT_VENC_CUR_CHROMA>,
+ < M4U_PORT_VENC_REF_LUMA>,
+ < M4U_PORT_VENC_REF_CHROMA>,
+ < M4U_PORT_VENC_NBM_RDMA>,
+ < M4U_PORT_VENC_NBM_WDMA>,
+ < M4U_PORT_VENC_RCPU_SET2>,
+ < M4U_PORT_VENC_REC_FRM_SET2>,
+ < M4U_PORT_VENC_BSDMA_SET2>,
+ < M4U_PORT_VENC_SV_COMA_SET2>,
+ < M4U_PORT_VENC_RD_COMA_SET2>,
+ < M4U_PORT_VENC_CUR_LUMA_SET2>,
+ < M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ < M4U_PORT_VENC_REF_LUMA_SET2>,
+ < M4U_PORT_VENC_REC_CHROMA_SET2>;
+mediatek,vpu = <>;
+clocks = < CLK_TOP_VENCPLL_D2>,
+ < CLK_TOP_VENC_SEL>,
+ < CLK_TOP_UNIVPLL1_D2>,
+ < CLK_TOP_VENC_LT_SEL>;
+clock-names = "venc_sel_src",
+  "venc_sel",
+  "venc_lt_sel_src",
+  "venc_lt_sel";
+  };
-- 
1.7.9.5



[PATCH v7 4/8] dt-bindings: Add a binding for Mediatek Video Encoder

2016-04-21 Thread Tiffany Lin
Add a DT binding documentation of Video Encoder for the
MT8173 SoC from Mediatek.

Signed-off-by: Tiffany Lin 
Acked-by: Rob Herring 

---
 .../devicetree/bindings/media/mediatek-vcodec.txt  |   59 
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec.txt

diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt 
b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
new file mode 100644
index 000..59a47a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
@@ -0,0 +1,59 @@
+Mediatek Video Codec
+
+Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
+supports high resolution encoding functionalities.
+
+Required properties:
+- compatible : "mediatek,mt8173-vcodec-enc" for encoder
+- reg : Physical base address of the video codec registers and length of
+  memory mapped region.
+- interrupts : interrupt number to the cpu.
+- mediatek,larb : must contain the local arbiters in the current Socs.
+- clocks : list of clock specifiers, corresponding to entries in
+  the clock-names property.
+- clock-names: encoder must contain "venc_sel_src", "venc_sel",
+- "venc_lt_sel_src", "venc_lt_sel".
+- iommus : should point to the respective IOMMU block with master port as
+  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+  for details.
+- mediatek,vpu : the node of video processor unit
+
+Example:
+vcodec_enc: vcodec@0x18002000 {
+compatible = "mediatek,mt8173-vcodec-enc";
+reg = <0 0x18002000 0 0x1000>,/*VENC_SYS*/
+  <0 0x19002000 0 0x1000>;/*VENC_LT_SYS*/
+interrupts = ,
+;
+mediatek,larb = <>,
+   <>;
+iommus = < M4U_PORT_VENC_RCPU>,
+ < M4U_PORT_VENC_REC>,
+ < M4U_PORT_VENC_BSDMA>,
+ < M4U_PORT_VENC_SV_COMV>,
+ < M4U_PORT_VENC_RD_COMV>,
+ < M4U_PORT_VENC_CUR_LUMA>,
+ < M4U_PORT_VENC_CUR_CHROMA>,
+ < M4U_PORT_VENC_REF_LUMA>,
+ < M4U_PORT_VENC_REF_CHROMA>,
+ < M4U_PORT_VENC_NBM_RDMA>,
+ < M4U_PORT_VENC_NBM_WDMA>,
+ < M4U_PORT_VENC_RCPU_SET2>,
+ < M4U_PORT_VENC_REC_FRM_SET2>,
+ < M4U_PORT_VENC_BSDMA_SET2>,
+ < M4U_PORT_VENC_SV_COMA_SET2>,
+ < M4U_PORT_VENC_RD_COMA_SET2>,
+ < M4U_PORT_VENC_CUR_LUMA_SET2>,
+ < M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ < M4U_PORT_VENC_REF_LUMA_SET2>,
+ < M4U_PORT_VENC_REC_CHROMA_SET2>;
+mediatek,vpu = <>;
+clocks = < CLK_TOP_VENCPLL_D2>,
+ < CLK_TOP_VENC_SEL>,
+ < CLK_TOP_UNIVPLL1_D2>,
+ < CLK_TOP_VENC_LT_SEL>;
+clock-names = "venc_sel_src",
+  "venc_sel",
+  "venc_lt_sel_src",
+  "venc_lt_sel";
+  };
-- 
1.7.9.5