[PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing
These patches enable Intel Xeon Phi x200 feature to use MONITOR/MWAIT instruction in ring 3 (userspace) Patches set MSR 0x140 for all logical CPUs. Then expose it as CPU feature and introduces elf HWCAP capability for x86. Reference: https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait v8: Fixed commit messages Removed logging Used msr_set/clear_bit functions instesd of wrmsrl Fixed documentation Renamed HWCAP2_PHIR3MWAIT to HWCAP2_RING3MWAIT v7: Change order of the patches, with this code looks cleaner. Changed the name of MSR to MSR_MISC_FEATURE_ENABLES. Used Word 3 25th bit to expose feature. v6: v5: When phir3mwait=disable is cmdline switch off r3 mwait feature Fix typos v4: Wrapped the enabling code by CONFIG_X86_64 Add documentation for phir3mwait=disable cmdline switch Move probe_ function call from early_intel_init to intel_init Fixed commit messages v3: Included Daves and Thomas comments v2: Check MSR before wrmsrl Shortened names Used Word 3 for feature init_scattered_cpuid_features() Fixed commit messages Grzegorz Andrejczuk (4): x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit x86/elf: Use HWCAP2 to expose ring 3 MWAIT x86/cpufeature: Add PHIR3MWAIT to CPU features x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models Documentation/kernel-parameters.txt | 5 Documentation/x86/x86_64/boot-options.txt | 5 arch/x86/include/asm/cpufeatures.h| 2 +- arch/x86/include/asm/elf.h| 9 +++ arch/x86/include/asm/msr-index.h | 5 arch/x86/include/uapi/asm/hwcap2.h| 7 ++ arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kernel/cpu/intel.c | 39 +++ 8 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/uapi/asm/hwcap2.h -- 2.5.1
[PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing
These patches enable Intel Xeon Phi x200 feature to use MONITOR/MWAIT instruction in ring 3 (userspace) Patches set MSR 0x140 for all logical CPUs. Then expose it as CPU feature and introduces elf HWCAP capability for x86. Reference: https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait v8: Fixed commit messages Removed logging Used msr_set/clear_bit functions instesd of wrmsrl Fixed documentation Renamed HWCAP2_PHIR3MWAIT to HWCAP2_RING3MWAIT v7: Change order of the patches, with this code looks cleaner. Changed the name of MSR to MSR_MISC_FEATURE_ENABLES. Used Word 3 25th bit to expose feature. v6: v5: When phir3mwait=disable is cmdline switch off r3 mwait feature Fix typos v4: Wrapped the enabling code by CONFIG_X86_64 Add documentation for phir3mwait=disable cmdline switch Move probe_ function call from early_intel_init to intel_init Fixed commit messages v3: Included Daves and Thomas comments v2: Check MSR before wrmsrl Shortened names Used Word 3 for feature init_scattered_cpuid_features() Fixed commit messages Grzegorz Andrejczuk (4): x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit x86/elf: Use HWCAP2 to expose ring 3 MWAIT x86/cpufeature: Add PHIR3MWAIT to CPU features x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models Documentation/kernel-parameters.txt | 5 Documentation/x86/x86_64/boot-options.txt | 5 arch/x86/include/asm/cpufeatures.h| 2 +- arch/x86/include/asm/elf.h| 9 +++ arch/x86/include/asm/msr-index.h | 5 arch/x86/include/uapi/asm/hwcap2.h| 7 ++ arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kernel/cpu/intel.c | 39 +++ 8 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/uapi/asm/hwcap2.h -- 2.5.1
