[PATCH v8 06/10] clk: mediatek: Add MT2701 clock support

2016-05-16 Thread Erin Lo 
From: Shunli Wang 

Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
---
 drivers/clk/mediatek/Kconfig   |   50 ++
 drivers/clk/mediatek/Makefile  |7 +
 drivers/clk/mediatek/clk-gate.c|   52 ++
 drivers/clk/mediatek/clk-gate.h|2 +
 drivers/clk/mediatek/clk-mt2701-bdp.c  |  140 +
 drivers/clk/mediatek/clk-mt2701-eth.c  |   82 +++
 drivers/clk/mediatek/clk-mt2701-hif.c  |   79 +++
 drivers/clk/mediatek/clk-mt2701-img.c  |   82 +++
 drivers/clk/mediatek/clk-mt2701-mm.c   |  125 
 drivers/clk/mediatek/clk-mt2701-vdec.c |   93 +++
 drivers/clk/mediatek/clk-mt2701.c  | 1033 
 drivers/clk/mediatek/clk-mtk.c |   40 ++
 drivers/clk/mediatek/clk-mtk.h |   52 +-
 drivers/clk/mediatek/clk-pll.c |1 +
 14 files changed, 1833 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt2701-bdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-eth.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-hif.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index dc224e6..5aa6204 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -6,6 +6,56 @@ config COMMON_CLK_MEDIATEK
---help---
  Mediatek SoCs' clock support.
 
+config COMMON_CLK_MT2701
+   bool "Clock driver for Mediatek MT2701"
+   depends on COMMON_CLK
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT2701 basic clocks.
+
+config COMMON_CLK_MT2701_MMSYS
+   bool "Clock driver for Mediatek MT2701 mmsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 mmsys clocks.
+
+config COMMON_CLK_MT2701_IMGSYS
+   bool "Clock driver for Mediatek MT2701 imgsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 imgsys clocks.
+
+config COMMON_CLK_MT2701_VDECSYS
+   bool "Clock driver for Mediatek MT2701 vdecsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 vdecsys clocks.
+
+config COMMON_CLK_MT2701_HIFSYS
+   bool "Clock driver for Mediatek MT2701 hifsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 hifsys clocks.
+
+config COMMON_CLK_MT2701_ETHSYS
+   bool "Clock driver for Mediatek MT2701 ethsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 ethsys clocks.
+
+config COMMON_CLK_MT2701_BDPSYS
+   bool "Clock driver for Mediatek MT2701 bdpsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 bdpsys clocks.
+
 config COMMON_CLK_MT8135
bool "Clock driver for Mediatek MT8135"
depends on COMMON_CLK
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 32e7222..19ae7ef 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,11 @@
 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o 
clk-apmixed.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
+obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
+obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
+obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
+obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
+obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index d8787bf..934bf0e 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -61,6 +61,22 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
 }
 
+static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
+{
+   struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+   u32 cgbit = BIT(cg->bit);
+
+   regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
+}
+
+static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
+{
+   struct mtk_clk_gate *cg =

[PATCH v8 06/10] clk: mediatek: Add MT2701 clock support

2016-05-16 Thread Erin Lo 
From: Shunli Wang 

Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang 
Signed-off-by: James Liao 
Tested-by: John Crispin 
---
 drivers/clk/mediatek/Kconfig   |   50 ++
 drivers/clk/mediatek/Makefile  |7 +
 drivers/clk/mediatek/clk-gate.c|   52 ++
 drivers/clk/mediatek/clk-gate.h|2 +
 drivers/clk/mediatek/clk-mt2701-bdp.c  |  140 +
 drivers/clk/mediatek/clk-mt2701-eth.c  |   82 +++
 drivers/clk/mediatek/clk-mt2701-hif.c  |   79 +++
 drivers/clk/mediatek/clk-mt2701-img.c  |   82 +++
 drivers/clk/mediatek/clk-mt2701-mm.c   |  125 
 drivers/clk/mediatek/clk-mt2701-vdec.c |   93 +++
 drivers/clk/mediatek/clk-mt2701.c  | 1033 
 drivers/clk/mediatek/clk-mtk.c |   40 ++
 drivers/clk/mediatek/clk-mtk.h |   52 +-
 drivers/clk/mediatek/clk-pll.c |1 +
 14 files changed, 1833 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt2701-bdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-eth.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-hif.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt2701.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index dc224e6..5aa6204 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -6,6 +6,56 @@ config COMMON_CLK_MEDIATEK
---help---
  Mediatek SoCs' clock support.
 
+config COMMON_CLK_MT2701
+   bool "Clock driver for Mediatek MT2701"
+   depends on COMMON_CLK
+   select COMMON_CLK_MEDIATEK
+   default ARCH_MEDIATEK
+   ---help---
+ This driver supports Mediatek MT2701 basic clocks.
+
+config COMMON_CLK_MT2701_MMSYS
+   bool "Clock driver for Mediatek MT2701 mmsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 mmsys clocks.
+
+config COMMON_CLK_MT2701_IMGSYS
+   bool "Clock driver for Mediatek MT2701 imgsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 imgsys clocks.
+
+config COMMON_CLK_MT2701_VDECSYS
+   bool "Clock driver for Mediatek MT2701 vdecsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 vdecsys clocks.
+
+config COMMON_CLK_MT2701_HIFSYS
+   bool "Clock driver for Mediatek MT2701 hifsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 hifsys clocks.
+
+config COMMON_CLK_MT2701_ETHSYS
+   bool "Clock driver for Mediatek MT2701 ethsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 ethsys clocks.
+
+config COMMON_CLK_MT2701_BDPSYS
+   bool "Clock driver for Mediatek MT2701 bdpsys"
+   depends on COMMON_CLK
+   select COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 bdpsys clocks.
+
 config COMMON_CLK_MT8135
bool "Clock driver for Mediatek MT8135"
depends on COMMON_CLK
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 32e7222..19ae7ef 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,4 +1,11 @@
 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o 
clk-apmixed.o
 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
+obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
+obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
+obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
+obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
+obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index d8787bf..934bf0e 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -61,6 +61,22 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
 }
 
+static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
+{
+   struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+   u32 cgbit = BIT(cg->bit);
+
+   regmap_update_bits(cg->regmap, cg->sta_ofs, cgbit, cgbit);
+}
+
+static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
+{
+   struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
+   u32 cgbit = BIT(cg->bit);
+
+   regmap_update_bits(cg->regmap,