subject:"\[PATCH v8 2\/3\] \[media\] rc\: add sunxi\-ir driver"

Re: [PATCH v8 2/3] [media] rc: add sunxi-ir driver

2014-06-01 Thread Maxime Ripard

On Mon, May 26, 2014 at 04:26:44AM +0600, Alexander Bersenev wrote:
> This patch adds driver for sunxi IR controller.
> It is based on Alexsey Shestacov's work based on the original driver
> supplied by Allwinner.
> 
> Signed-off-by: Alexander Bersenev 
> Signed-off-by: Alexsey Shestacov 
> ---
>  drivers/media/rc/Kconfig |  10 ++
>  drivers/media/rc/Makefile|   1 +
>  drivers/media/rc/sunxi-cir.c | 313 
> +++
>  3 files changed, 324 insertions(+)
>  create mode 100644 drivers/media/rc/sunxi-cir.c
> 
> diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
> index 8fbd377..9427fad 100644
> --- a/drivers/media/rc/Kconfig
> +++ b/drivers/media/rc/Kconfig
> @@ -343,4 +343,14 @@ config RC_ST
>  
>If you're not sure, select N here.
>  
> +config IR_SUNXI
> +tristate "SUNXI IR remote control"
> +depends on RC_CORE
> +depends on ARCH_SUNXI
> +---help---
> +  Say Y if you want to use sunXi internal IR Controller
> +
> +  To compile this driver as a module, choose M here: the module will
> +  be called sunxi-ir.
> +
>  endif #RC_DEVICES
> diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
> index f8b54ff..9ee9ee7 100644
> --- a/drivers/media/rc/Makefile
> +++ b/drivers/media/rc/Makefile
> @@ -32,4 +32,5 @@ obj-$(CONFIG_IR_GPIO_CIR) += gpio-ir-recv.o
>  obj-$(CONFIG_IR_IGUANA) += iguanair.o
>  obj-$(CONFIG_IR_TTUSBIR) += ttusbir.o
>  obj-$(CONFIG_RC_ST) += st_rc.o
> +obj-$(CONFIG_IR_SUNXI) += sunxi-cir.o
>  obj-$(CONFIG_IR_IMG) += img-ir/
> diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> new file mode 100644
> index 000..245d8dc
> --- /dev/null
> +++ b/drivers/media/rc/sunxi-cir.c
> @@ -0,0 +1,313 @@
> +/*
> + * Driver for Allwinner sunXi IR controller
> + *
> + * Copyright (C) 2014 Alexsey Shestacov 
> + * Copyright (C) 2014 Alexander Bersenev 
> + *
> + * Based on sun5i-ir.c:
> + * Copyright (C) 2007-2012 Daniel Wang
> + * Allwinner Technology Co., Ltd. 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define SUNXI_IR_DEV "sunxi-ir"
> +
> +/* Registers */
> +/* IR Control */
> +#define SUNXI_IR_CTL_REG  0x00
> +#define REG_CTL_GEN   BIT(0) /* Global Enable */
> +#define REG_CTL_RXEN  BIT(1) /* RX block enable */
> +#define REG_CTL_MD(BIT(4)|BIT(5)) /* CIR mode */

You should have a space around the operator here, and one more level
of indentation for the bits definition would be nice.

> +
> +/* Rx Config */
> +#define SUNXI_IR_RXCTL_REG0x10
> +#define REG_RXCTL_RPPIBIT(2) /* Pulse Polarity Invert flag */
> +
> +/* Rx Data */
> +#define SUNXI_IR_RXFIFO_REG   0x20
> +
> +/* Rx Interrupt Enable */
> +#define SUNXI_IR_RXINT_REG0x2C
> +#define REG_RXINT_ROI_EN  BIT(0) /* Rx FIFO Overflow */
> +#define REG_RXINT_RPEI_EN BIT(1) /* Rx Packet End */
> +#define REG_RXINT_RAI_EN  BIT(4) /* Rx FIFO Data Available */
> +/* Rx FIFO available byte level */

Either put the comments on the same line or on the above line, but
please stick to the choice you're making

> +#define REG_RXINT_RAL(val)(((val) << 8) & 
> (BIT(8)|BIT(9)|BIT(10)|BIT(11)))

Just use the mask directly here, or the GENMASK macro.

> +
> +/* Rx Interrupt Status */
> +#define SUNXI_IR_RXSTA_REG0x30
> +/* RX FIFO Get Available Counter */
> +#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (BIT(0)|BIT(1)|BIT(2)|BIT(3) \
> +   |BIT(4)|BIT(5)))
> +/* Clear all interrupt status value */
> +#define REG_RXSTA_CLEARALL0xff
> +
> +/* IR Sample Config */
> +#define SUNXI_IR_CIR_REG  0x34
> +/* CIR_REG register noise threshold */
> +#define REG_CIR_NTHR(val)(((val) << 2) & (BIT(2)|BIT(3)|BIT(4)|BIT(5) \
> +  |BIT(6)|BIT(7)))
> +/* CIR_REG register idle threshold */
> +#define REG_CIR_ITHR(val)(((val) << 8) & (BIT(8)|BIT(9)|BIT(10)|BIT(11) \
> +  |BIT(12)|BIT(13)|BIT(14)|BIT(15)))
> +
> +/* Hardware supported fifo size */
> +#define SUNXI_IR_FIFO_SIZE16
> +/* How many messages in FIFO trigger IRQ */
> +#define TRIGGER_LEVEL 8
> +/* Required frequency for IR0 or IR1 clock in CIR mode */
> +#define SUNXI_IR_BASE_CLK 800
> +/* Frequency after IR internal divider  */
> +#define SUNXI_IR_CLK  (SUNXI_IR_BASE_CLK / 64)
> +/* Sample period in ns */
> +#define SUNXI_IR_SAMPLE   (10ul / SUNXI_IR_CL

[PATCH v8 2/3] [media] rc: add sunxi-ir driver

2014-05-25 Thread Alexander Bersenev

This patch adds driver for sunxi IR controller.
It is based on Alexsey Shestacov's work based on the original driver
supplied by Allwinner.

Signed-off-by: Alexander Bersenev 
Signed-off-by: Alexsey Shestacov 
---
 drivers/media/rc/Kconfig |  10 ++
 drivers/media/rc/Makefile|   1 +
 drivers/media/rc/sunxi-cir.c | 313 +++
 3 files changed, 324 insertions(+)
 create mode 100644 drivers/media/rc/sunxi-cir.c

diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 8fbd377..9427fad 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -343,4 +343,14 @@ config RC_ST
 
 If you're not sure, select N here.
 
+config IR_SUNXI
+tristate "SUNXI IR remote control"
+depends on RC_CORE
+depends on ARCH_SUNXI
+---help---
+  Say Y if you want to use sunXi internal IR Controller
+
+  To compile this driver as a module, choose M here: the module will
+  be called sunxi-ir.
+
 endif #RC_DEVICES
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index f8b54ff..9ee9ee7 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -32,4 +32,5 @@ obj-$(CONFIG_IR_GPIO_CIR) += gpio-ir-recv.o
 obj-$(CONFIG_IR_IGUANA) += iguanair.o
 obj-$(CONFIG_IR_TTUSBIR) += ttusbir.o
 obj-$(CONFIG_RC_ST) += st_rc.o
+obj-$(CONFIG_IR_SUNXI) += sunxi-cir.o
 obj-$(CONFIG_IR_IMG) += img-ir/
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
new file mode 100644
index 000..245d8dc
--- /dev/null
+++ b/drivers/media/rc/sunxi-cir.c
@@ -0,0 +1,313 @@
+/*
+ * Driver for Allwinner sunXi IR controller
+ *
+ * Copyright (C) 2014 Alexsey Shestacov 
+ * Copyright (C) 2014 Alexander Bersenev 
+ *
+ * Based on sun5i-ir.c:
+ * Copyright (C) 2007-2012 Daniel Wang
+ * Allwinner Technology Co., Ltd. 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SUNXI_IR_DEV "sunxi-ir"
+
+/* Registers */
+/* IR Control */
+#define SUNXI_IR_CTL_REG  0x00
+#define REG_CTL_GEN   BIT(0) /* Global Enable */
+#define REG_CTL_RXEN  BIT(1) /* RX block enable */
+#define REG_CTL_MD(BIT(4)|BIT(5)) /* CIR mode */
+
+/* Rx Config */
+#define SUNXI_IR_RXCTL_REG0x10
+#define REG_RXCTL_RPPIBIT(2) /* Pulse Polarity Invert flag */
+
+/* Rx Data */
+#define SUNXI_IR_RXFIFO_REG   0x20
+
+/* Rx Interrupt Enable */
+#define SUNXI_IR_RXINT_REG0x2C
+#define REG_RXINT_ROI_EN  BIT(0) /* Rx FIFO Overflow */
+#define REG_RXINT_RPEI_EN BIT(1) /* Rx Packet End */
+#define REG_RXINT_RAI_EN  BIT(4) /* Rx FIFO Data Available */
+/* Rx FIFO available byte level */
+#define REG_RXINT_RAL(val)(((val) << 8) & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
+
+/* Rx Interrupt Status */
+#define SUNXI_IR_RXSTA_REG0x30
+/* RX FIFO Get Available Counter */
+#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (BIT(0)|BIT(1)|BIT(2)|BIT(3) \
+ |BIT(4)|BIT(5)))
+/* Clear all interrupt status value */
+#define REG_RXSTA_CLEARALL0xff
+
+/* IR Sample Config */
+#define SUNXI_IR_CIR_REG  0x34
+/* CIR_REG register noise threshold */
+#define REG_CIR_NTHR(val)(((val) << 2) & (BIT(2)|BIT(3)|BIT(4)|BIT(5) \
+|BIT(6)|BIT(7)))
+/* CIR_REG register idle threshold */
+#define REG_CIR_ITHR(val)(((val) << 8) & (BIT(8)|BIT(9)|BIT(10)|BIT(11) \
+|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
+
+/* Hardware supported fifo size */
+#define SUNXI_IR_FIFO_SIZE16
+/* How many messages in FIFO trigger IRQ */
+#define TRIGGER_LEVEL 8
+/* Required frequency for IR0 or IR1 clock in CIR mode */
+#define SUNXI_IR_BASE_CLK 800
+/* Frequency after IR internal divider  */
+#define SUNXI_IR_CLK  (SUNXI_IR_BASE_CLK / 64)
+/* Sample period in ns */
+#define SUNXI_IR_SAMPLE   (10ul / SUNXI_IR_CLK)
+/* Noise threshold in samples  */
+#define SUNXI_IR_RXNOISE  1
+/* Idle Threshold in samples */
+#define SUNXI_IR_RXIDLE   20
+/* Time after which device stops sending data in ms */
+#define SUNXI_IR_TIMEOUT  120
+
+struct sunxi_ir {
+   spinlock_t  ir_lock;
+   struct rc_dev   *rc;
+   void __iomem*base;
+   int irq;
+   struct clk  *clk;
+   struct clk  *apb_clk;
+   const char  *map_name;
+};
+
+static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
+{
+   unsigned long status;
+   unsigned char dt;
+   unsigned

Re: [PATCH v8 2/3] [media] rc: add sunxi-ir driver

[PATCH v8 2/3] [media] rc: add sunxi-ir driver

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