[PATCH v8 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhran Signed-off-by: Vyacheslav Tyrtov Acked-by: Tomasz Figa --- .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 223 include/dt-bindings/clock/exynos5410.h | 33 +++ 4 files changed, 308 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt new file mode 100644 index 000..82337c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt @@ -0,0 +1,51 @@ +* Samsung Exynos5410 Clock Controller + +The Exynos5410 clock controller generates and supplies clock to various +controllers within the Exynos5410 SoC. + +Required Properties: + +- compatible: should be "samsung,exynos5410-clock" + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5410.h header and can be used in device +tree sources. + +External clock: +There is clock that is generated outside the SoC. It is expected +that it is defined using standard clock bindings with following + - compatible: should be "samsung,exynos5410-oscclk" + +Example 1: An example of a clock controller node is listed below. + + clock: clock-controller@0x1001 { + compatible = "samsung,exynos5410-clock"; + reg = <0x1001 0x3>; + #clock-cells = <1>; + }; + +Example 2: Required external clock. + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5410-oscclk"; + clock-frequency = <2400>; + }; + }; + +Example 3: UART controller node that consumes the clock generated by the clock + controller. Refer to the standard clock bindings for information + about 'clocks' and 'clock-names' property. + + serial@12C2 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C0 0x100>; + interrupts = <0 51 0>; + clocks = < CLK_UART0>, < CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + }; diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..b572dd7 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c new file mode 100644 index 000..7fdc17a --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Tarek Dakhran + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5410 SoC. +*/ + +#include + +#include +#include +#include +#include +#include + +#include "clk.h" + +#define APLL_LOCK 0x0 +#define APLL_CON0 0x100 +#define CPLL_LOCK 0x10020 +#define CPLL_CON0 0x10120 +#define MPLL_LOCK 0x4000 +#define MPLL_CON0 0x4100 +#define BPLL_LOCK 0x20010 +#define BPLL_CON0 0x20110 +#define KPLL_LOCK 0x28000 +#define KPLL_CON0 0x28100 + +#define SRC_CPU0x200 +#define DIV_CPU0 0x500 +#define SRC_CPERI1 0x4204 +#define DIV_TOP0 0x10510 +#define DIV_TOP1 0x10514 +#define DIV_FSYS1 0x1054c +#define DIV_FSYS2 0x10550 +#define DIV_PERIC0 0x10558 +#define SRC_TOP0 0x10210 +#define SRC_TOP1 0x10214 +#define SRC_TOP2 0x10218 +#define SRC_FSYS 0x10244 +#define SRC_PERIC0 0x10250 +#define SRC_MASK_FSYS 0x10340 +#define SRC_MASK_PERIC00x10350 +#define GATE_BUS_FSYS0 0x10740 +#define GATE_IP_FSYS 0x10944 +#define
[PATCH v8 2/3] clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com Acked-by: Tomasz Figa t.f...@samsung.com --- .../devicetree/bindings/clock/exynos5410-clock.txt | 51 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5410.c | 223 include/dt-bindings/clock/exynos5410.h | 33 +++ 4 files changed, 308 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt new file mode 100644 index 000..82337c4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt @@ -0,0 +1,51 @@ +* Samsung Exynos5410 Clock Controller + +The Exynos5410 clock controller generates and supplies clock to various +controllers within the Exynos5410 SoC. + +Required Properties: + +- compatible: should be samsung,exynos5410-clock + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5410.h header and can be used in device +tree sources. + +External clock: +There is clock that is generated outside the SoC. It is expected +that it is defined using standard clock bindings with following + - compatible: should be samsung,exynos5410-oscclk + +Example 1: An example of a clock controller node is listed below. + + clock: clock-controller@0x1001 { + compatible = samsung,exynos5410-clock; + reg = 0x1001 0x3; + #clock-cells = 1; + }; + +Example 2: Required external clock. + + fixed-rate-clocks { + oscclk { + compatible = samsung,exynos5410-oscclk; + clock-frequency = 2400; + }; + }; + +Example 3: UART controller node that consumes the clock generated by the clock + controller. Refer to the standard clock bindings for information + about 'clocks' and 'clock-names' property. + + serial@12C2 { + compatible = samsung,exynos4210-uart; + reg = 0x12C0 0x100; + interrupts = 0 51 0; + clocks = clock CLK_UART0, clock CLK_SCLK_UART0; + clock-names = uart, clk_uart_baud0; + }; diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..b572dd7 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c new file mode 100644 index 000..7fdc17a --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Tarek Dakhran t.dakh...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5410 SoC. +*/ + +#include dt-bindings/clock/exynos5410.h + +#include linux/clk.h +#include linux/clkdev.h +#include linux/clk-provider.h +#include linux/of.h +#include linux/of_address.h + +#include clk.h + +#define APLL_LOCK 0x0 +#define APLL_CON0 0x100 +#define CPLL_LOCK 0x10020 +#define CPLL_CON0 0x10120 +#define MPLL_LOCK 0x4000 +#define MPLL_CON0 0x4100 +#define BPLL_LOCK 0x20010 +#define BPLL_CON0 0x20110 +#define KPLL_LOCK 0x28000 +#define KPLL_CON0 0x28100 + +#define SRC_CPU0x200 +#define DIV_CPU0 0x500 +#define SRC_CPERI1 0x4204 +#define DIV_TOP0 0x10510 +#define DIV_TOP1 0x10514 +#define DIV_FSYS1 0x1054c +#define DIV_FSYS2 0x10550 +#define DIV_PERIC0 0x10558 +#define SRC_TOP0 0x10210 +#define SRC_TOP1 0x10214 +#define SRC_TOP2 0x10218 +#define SRC_FSYS 0x10244 +#define SRC_PERIC0 0x10250 +#define