[RESEND PATCH v8 2/3] dt-bindings: phy: Add YAML schemas for Intel ComboPhy
ComboPhy subsystem provides PHY support to various
controllers, viz. PCIe, SATA and EMAC.
Adding YAML schemas for the same.
Signed-off-by: Dilip Kota
Reviewed-by: Rob Herring
---
Changes on v8:
No Change.
Changes on v7:
No Change.
Changes on v6:
Add Reviewed-by: Rob Herring
.../devicetree/bindings/phy/intel,combo-phy.yaml | 101 +
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
b/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
new file mode 100644
index ..347d0cdfb80d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel ComboPhy Subsystem
+
+maintainers:
+ - Dilip Kota
+
+description: |
+ Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
+ controllers. A single Combophy provides two PHY instances.
+
+properties:
+ $nodename:
+pattern: "combophy(@.*|-[0-9a-f])*$"
+
+ compatible:
+items:
+ - const: intel,combophy-lgm
+ - const: intel,combo-phy
+
+ clocks:
+maxItems: 1
+
+ reg:
+items:
+ - description: ComboPhy core registers
+ - description: PCIe app core control registers
+
+ reg-names:
+items:
+ - const: core
+ - const: app
+
+ resets:
+maxItems: 4
+
+ reset-names:
+items:
+ - const: phy
+ - const: core
+ - const: iphy0
+ - const: iphy1
+
+ intel,syscfg:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+description: Chip configuration registers handle and ComboPhy instance id
+
+ intel,hsio:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+description: HSIO registers handle and ComboPhy instance id on NOC
+
+ intel,aggregation:
+type: boolean
+description: |
+ Specify the flag to configure ComboPHY in dual lane mode.
+
+ intel,phy-mode:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: |
+ Mode of the two phys in ComboPhy.
+ See dt-bindings/phy/phy.h for values.
+
+ "#phy-cells":
+const: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - intel,syscfg
+ - intel,hsio
+ - intel,phy-mode
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+combophy@d0a0 {
+compatible = "intel,combophy-lgm", "intel,combo-phy";
+clocks = < 1>;
+#phy-cells = <1>;
+reg = <0xd0a0 0x4>,
+ <0xd0a4 0x1000>;
+reg-names = "core", "app";
+resets = < 0x50 6>,
+ < 0x50 17>,
+ < 0x50 23>,
+ < 0x50 24>;
+reset-names = "phy", "core", "iphy0", "iphy1";
+intel,syscfg = < 0>;
+intel,hsio = < 0>;
+intel,phy-mode = ;
+intel,aggregation;
+};
--
2.11.0
[PATCH v8 2/3] dt-bindings: phy: Add YAML schemas for Intel ComboPhy
ComboPhy subsystem provides PHY support to various
controllers, viz. PCIe, SATA and EMAC.
Adding YAML schemas for the same.
Signed-off-by: Dilip Kota
Reviewed-by: Rob Herring
---
Changes on v8:
No Change.
Changes on v7:
No Change.
Changes on v6:
Add Reviewed-by: Rob Herring
.../devicetree/bindings/phy/intel,combo-phy.yaml | 101 +
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
b/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
new file mode 100644
index ..347d0cdfb80d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel ComboPhy Subsystem
+
+maintainers:
+ - Dilip Kota
+
+description: |
+ Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
+ controllers. A single Combophy provides two PHY instances.
+
+properties:
+ $nodename:
+pattern: "combophy(@.*|-[0-9a-f])*$"
+
+ compatible:
+items:
+ - const: intel,combophy-lgm
+ - const: intel,combo-phy
+
+ clocks:
+maxItems: 1
+
+ reg:
+items:
+ - description: ComboPhy core registers
+ - description: PCIe app core control registers
+
+ reg-names:
+items:
+ - const: core
+ - const: app
+
+ resets:
+maxItems: 4
+
+ reset-names:
+items:
+ - const: phy
+ - const: core
+ - const: iphy0
+ - const: iphy1
+
+ intel,syscfg:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+description: Chip configuration registers handle and ComboPhy instance id
+
+ intel,hsio:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+description: HSIO registers handle and ComboPhy instance id on NOC
+
+ intel,aggregation:
+type: boolean
+description: |
+ Specify the flag to configure ComboPHY in dual lane mode.
+
+ intel,phy-mode:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: |
+ Mode of the two phys in ComboPhy.
+ See dt-bindings/phy/phy.h for values.
+
+ "#phy-cells":
+const: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - intel,syscfg
+ - intel,hsio
+ - intel,phy-mode
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+combophy@d0a0 {
+compatible = "intel,combophy-lgm", "intel,combo-phy";
+clocks = < 1>;
+#phy-cells = <1>;
+reg = <0xd0a0 0x4>,
+ <0xd0a4 0x1000>;
+reg-names = "core", "app";
+resets = < 0x50 6>,
+ < 0x50 17>,
+ < 0x50 23>,
+ < 0x50 24>;
+reset-names = "phy", "core", "iphy0", "iphy1";
+intel,syscfg = < 0>;
+intel,hsio = < 0>;
+intel,phy-mode = ;
+intel,aggregation;
+};
--
2.11.0
