Re: [PATCH v8 5/5] arm: dts: add new device nodes to NPCM750 device tree EVB

[Joel Stanley]

On Tue, 29 Sep 2020 at 13:18, Tomer Maimon  wrote:
>
> Add the following new device nodes to
> NPCM750 evolution board device tree:
>
> - NPCM7xx Pin controller and GPIO
> - NPCM7xx PWM and FAN.
> - NPCM7xx EHCI USB.
> - NPCM7xx KCS.
> - NPCM Reset.
> - NPCM Peripheral SPI.
> - NPCM FIU SPI.
> - NPCM HWRNG.
> - NPCM I2C.
> - STMicro STMMAC.
>
> Signed-off-by: Tomer Maimon 

Reviewed-by: Joel Stanley 

> ---
>  arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 367 +-
>  .../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi  | 157 
>  2 files changed, 523 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi
>
> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts 
> b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> index 15f744f1beea..9f13d08f5804 100644
> --- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> @@ -4,24 +4,161 @@
>
>  /dts-v1/;
>  #include "nuvoton-npcm750.dtsi"
> +#include "dt-bindings/gpio/gpio.h"
> +#include "nuvoton-npcm750-pincfg-evb.dtsi"
>
>  / {
> model = "Nuvoton npcm750 Development Board (Device Tree)";
> compatible = "nuvoton,npcm750";
>
> +   aliases {
> +   ethernet2 = &gmac0;
> +   ethernet3 = &gmac1;
> +   serial0 = &serial0;
> +   serial1 = &serial1;
> +   serial2 = &serial2;
> +   serial3 = &serial3;
> +   i2c0 = &i2c0;
> +   i2c1 = &i2c1;
> +   i2c2 = &i2c2;
> +   i2c3 = &i2c3;
> +   i2c4 = &i2c4;
> +   i2c5 = &i2c5;
> +   i2c6 = &i2c6;
> +   i2c7 = &i2c7;
> +   i2c8 = &i2c8;
> +   i2c9 = &i2c9;
> +   i2c10 = &i2c10;
> +   i2c11 = &i2c11;
> +   i2c12 = &i2c12;
> +   i2c13 = &i2c13;
> +   i2c14 = &i2c14;
> +   i2c15 = &i2c15;
> +   spi0 = &spi0;
> +   spi1 = &spi1;
> +   fiu0 = &fiu0;
> +   fiu1 = &fiu3;
> +   fiu2 = &fiux;
> +   };
> +
> chosen {
> stdout-path = &serial3;
> };
>
> memory {
> -   reg = <0 0x4000>;
> +   device_type = "memory";
> +   reg = <0x0 0x2000>;
> +   };
> +};
> +
> +&gmac0 {
> +   phy-mode = "rgmii-id";
> +   status = "okay";
> +};
> +
> +&gmac1 {
> +   phy-mode = "rgmii-id";
> +   status = "okay";
> +};
> +
> +&ehci1 {
> +   status = "okay";
> +};
> +
> +&fiu0 {
> +   status = "okay";
> +   spi-nor@0 {
> +   compatible = "jedec,spi-nor";
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   spi-rx-bus-width = <2>;
> +   reg = <0>;
> +   spi-max-frequency = <500>;
> +   partitions@8000 {
> +   compatible = "fixed-partitions";
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   bbuboot1@0 {
> +   label = "bb-uboot-1";
> +   reg = <0x000 0x8>;
> +   read-only;
> +   };
> +   bbuboot2@8 {
> +   label = "bb-uboot-2";
> +   reg = <0x008 0x8>;
> +   read-only;
> +   };
> +   envparam@10 {
> +   label = "env-param";
> +   reg = <0x010 0x4>;
> +   read-only;
> +   };
> +   spare@14 {
> +   label = "spare";
> +   reg = <0x014 0xC>;
> +   };
> +   kernel@20 {
> +   label = "kernel";
> +   reg = <0x020 0x40>;
> +   };
> +   rootfs@60 {
> +   label = "rootfs";
> +   reg = <0x060 0x70>;
> +   };
> +   spare1@D0 {
> +   label = "spare1";
> +   reg = <0x0D0 0x20>;
> +   };
> +   spare2@0F0 {
> +   label = "spare2";
> +   reg = <0x0F0 0x20>;
> +   };
> +   spare3@110 {
> +   label = "spare3";
> +   reg =

[PATCH v8 5/5] arm: dts: add new device nodes to NPCM750 device tree EVB

[Tomer Maimon]

Add the following new device nodes to
NPCM750 evolution board device tree:

- NPCM7xx Pin controller and GPIO
- NPCM7xx PWM and FAN.
- NPCM7xx EHCI USB.
- NPCM7xx KCS.
- NPCM Reset.
- NPCM Peripheral SPI.
- NPCM FIU SPI.
- NPCM HWRNG.
- NPCM I2C.
- STMicro STMMAC.

Signed-off-by: Tomer Maimon 
---
 arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 367 +-
 .../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi  | 157 
 2 files changed, 523 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi

diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts 
b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
index 15f744f1beea..9f13d08f5804 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -4,24 +4,161 @@
 
 /dts-v1/;
 #include "nuvoton-npcm750.dtsi"
+#include "dt-bindings/gpio/gpio.h"
+#include "nuvoton-npcm750-pincfg-evb.dtsi"
 
 / {
model = "Nuvoton npcm750 Development Board (Device Tree)";
compatible = "nuvoton,npcm750";
 
+   aliases {
+   ethernet2 = &gmac0;
+   ethernet3 = &gmac1;
+   serial0 = &serial0;
+   serial1 = &serial1;
+   serial2 = &serial2;
+   serial3 = &serial3;
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   i2c2 = &i2c2;
+   i2c3 = &i2c3;
+   i2c4 = &i2c4;
+   i2c5 = &i2c5;
+   i2c6 = &i2c6;
+   i2c7 = &i2c7;
+   i2c8 = &i2c8;
+   i2c9 = &i2c9;
+   i2c10 = &i2c10;
+   i2c11 = &i2c11;
+   i2c12 = &i2c12;
+   i2c13 = &i2c13;
+   i2c14 = &i2c14;
+   i2c15 = &i2c15;
+   spi0 = &spi0;
+   spi1 = &spi1;
+   fiu0 = &fiu0;
+   fiu1 = &fiu3;
+   fiu2 = &fiux;
+   };
+
chosen {
stdout-path = &serial3;
};
 
memory {
-   reg = <0 0x4000>;
+   device_type = "memory";
+   reg = <0x0 0x2000>;
+   };
+};
+
+&gmac0 {
+   phy-mode = "rgmii-id";
+   status = "okay";
+};
+
+&gmac1 {
+   phy-mode = "rgmii-id";
+   status = "okay";
+};
+
+&ehci1 {
+   status = "okay";
+};
+
+&fiu0 {
+   status = "okay";
+   spi-nor@0 {
+   compatible = "jedec,spi-nor";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   spi-rx-bus-width = <2>;
+   reg = <0>;
+   spi-max-frequency = <500>;
+   partitions@8000 {
+   compatible = "fixed-partitions";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   bbuboot1@0 {
+   label = "bb-uboot-1";
+   reg = <0x000 0x8>;
+   read-only;
+   };
+   bbuboot2@8 {
+   label = "bb-uboot-2";
+   reg = <0x008 0x8>;
+   read-only;
+   };
+   envparam@10 {
+   label = "env-param";
+   reg = <0x010 0x4>;
+   read-only;
+   };
+   spare@14 {
+   label = "spare";
+   reg = <0x014 0xC>;
+   };
+   kernel@20 {
+   label = "kernel";
+   reg = <0x020 0x40>;
+   };
+   rootfs@60 {
+   label = "rootfs";
+   reg = <0x060 0x70>;
+   };
+   spare1@D0 {
+   label = "spare1";
+   reg = <0x0D0 0x20>;
+   };
+   spare2@0F0 {
+   label = "spare2";
+   reg = <0x0F0 0x20>;
+   };
+   spare3@110 {
+   label = "spare3";
+   reg = <0x110 0x20>;
+   };
+   spare4@130 {
+   label = "spare4";
+   reg = <0x130 0x0>;
+   };
+   };
+   };
+};
+
+&fiu3 {
+   pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
+   status = "okay";
+