Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-06-03 Thread Bintian 

On 2015/6/4 6:39, Michael Turquette wrote:

Quoting Bintian Wang (2015-05-28 19:08:38)

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz 
Signed-off-by: Bintian Wang 
Acked-by: Haojian Zhuang 
Reviewed-by: Zhangfei Gao 
Tested-by: Will Deacon 
Tested-by: Tyler Baker 
Tested-by: Kevin Hilman 


I've applied patches #4-6 to the clk tree.


Thank you Mike.

Best Regards,

Bintian


Regards,
Mike


---
  drivers/clk/Kconfig   |   1 +
  drivers/clk/Makefile  |   4 +-
  drivers/clk/hisilicon/Kconfig |   6 +
  drivers/clk/hisilicon/Makefile|   3 +-
  drivers/clk/hisilicon/clk-hi6220.c| 284 ++
  drivers/clk/hisilicon/clk.c   |  29 +++
  drivers/clk/hisilicon/clk.h   |  17 ++
  drivers/clk/hisilicon/clkdivider-hi6220.c | 156 
  8 files changed, 496 insertions(+), 4 deletions(-)
  create mode 100644 drivers/clk/hisilicon/Kconfig
  create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
  create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
   This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.

  source "drivers/clk/bcm/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
  source "drivers/clk/qcom/Kconfig"

  endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)  += clk-pwm.o
  obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
  obj-$(CONFIG_ARCH_BCM_MOBILE)  += bcm/
  obj-$(CONFIG_ARCH_BERLIN)  += berlin/
-obj-$(CONFIG_ARCH_HI3xxx)  += hisilicon/
-obj-$(CONFIG_ARCH_HIP04)   += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
  obj-$(CONFIG_ARCH_MXC) += imx/
  obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
  obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+   bool "Hi6220 Clock Driver"
+   depends on ARCH_HISI || COMPILE_TEST
+   default ARCH_HISI
+   help
+ Build the Hisilicon Hi6220 clock driver based on the common clock 
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
  # Hisilicon Clock specific Makefile
  #

-obj-y  += clk.o clkgate-separated.o
+obj-y  += clk.o clkgate-separated.o clkdivider-hi6220.o

  obj-$(CONFIG_ARCH_HI3xxx)  += clk-hi3620.o
  obj-$(CONFIG_ARCH_HIP04)   += clk-hip04.o
  obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+   { HI6220_REF32K,"ref32k",   NULL, CLK_IS_ROOT, 32764, },
+   { HI6220_CLK_TCXO,  "clk_tcxo", NULL, CLK_IS_ROOT, 1920,  },
+   { HI6220_MMC1_PAD,  "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC2_PAD,  "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC0_PAD,  "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+   { HI6220_PLL_BBP,   "bbppll0",  NULL, CLK_IS_ROOT, 24576, },
+   { HI6220_PLL_GPU,   "gpupll",   NULL, CLK_IS_ROOT, 10,},
+   { HI6220_PLL1_DDR,  "ddrpll1",  NULL, CLK_IS_ROOT, 106600,},
+   {

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-06-03 Thread Michael Turquette 
Quoting Bintian Wang (2015-05-28 19:08:38)
> Add clock drivers for hi6220 SoC, this driver controls the SoC
> registers to supply different clocks to different IPs in the SoC.
> 
> We add one divider clock for hi6220 because the divider in hi6220
> also has a mask bit but it doesnot obey the rule defined by flag
> "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
> left shift fixed bits (e.g. 16 bits), so we add this divider clock
> to handle it.
> 
> Signed-off-by: Jorge Ramirez-Ortiz 
> Signed-off-by: Bintian Wang 
> Acked-by: Haojian Zhuang 
> Reviewed-by: Zhangfei Gao 
> Tested-by: Will Deacon 
> Tested-by: Tyler Baker 
> Tested-by: Kevin Hilman 

I've applied patches #4-6 to the clk tree.

Regards,
Mike

> ---
>  drivers/clk/Kconfig   |   1 +
>  drivers/clk/Makefile  |   4 +-
>  drivers/clk/hisilicon/Kconfig |   6 +
>  drivers/clk/hisilicon/Makefile|   3 +-
>  drivers/clk/hisilicon/clk-hi6220.c| 284 
> ++
>  drivers/clk/hisilicon/clk.c   |  29 +++
>  drivers/clk/hisilicon/clk.h   |  17 ++
>  drivers/clk/hisilicon/clkdivider-hi6220.c | 156 
>  8 files changed, 496 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/clk/hisilicon/Kconfig
>  create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
>  create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index de8c58f..cd6029d4 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
>   This driver supports TI CDCE706 programmable 3-PLL clock 
> synthesizer.
>  
>  source "drivers/clk/bcm/Kconfig"
> +source "drivers/clk/hisilicon/Kconfig"
>  source "drivers/clk/qcom/Kconfig"
>  
>  endmenu
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index d2d5e6c..440ef72 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)  += clk-pwm.o
>  obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
>  obj-$(CONFIG_ARCH_BCM_MOBILE)  += bcm/
>  obj-$(CONFIG_ARCH_BERLIN)  += berlin/
> -obj-$(CONFIG_ARCH_HI3xxx)  += hisilicon/
> -obj-$(CONFIG_ARCH_HIP04)   += hisilicon/
> -obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
> +obj-$(CONFIG_ARCH_HISI)+= hisilicon/
>  obj-$(CONFIG_ARCH_MXC) += imx/
>  obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
>  obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
> new file mode 100644
> index 000..b4165ba
> --- /dev/null
> +++ b/drivers/clk/hisilicon/Kconfig
> @@ -0,0 +1,6 @@
> +config COMMON_CLK_HI6220
> +   bool "Hi6220 Clock Driver"
> +   depends on ARCH_HISI || COMPILE_TEST
> +   default ARCH_HISI
> +   help
> + Build the Hisilicon Hi6220 clock driver based on the common clock 
> framework.
> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
> index 038c02f..48f0116 100644
> --- a/drivers/clk/hisilicon/Makefile
> +++ b/drivers/clk/hisilicon/Makefile
> @@ -2,8 +2,9 @@
>  # Hisilicon Clock specific Makefile
>  #
>  
> -obj-y  += clk.o clkgate-separated.o
> +obj-y  += clk.o clkgate-separated.o clkdivider-hi6220.o
>  
>  obj-$(CONFIG_ARCH_HI3xxx)  += clk-hi3620.o
>  obj-$(CONFIG_ARCH_HIP04)   += clk-hip04.o
>  obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
> +obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
> diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
> b/drivers/clk/hisilicon/clk-hi6220.c
> new file mode 100644
> index 000..4563343
> --- /dev/null
> +++ b/drivers/clk/hisilicon/clk-hi6220.c
> @@ -0,0 +1,284 @@
> +/*
> + * Hisilicon Hi6220 clock driver
> + *
> + * Copyright (c) 2015 Hisilicon Limited.
> + *
> + * Author: Bintian Wang 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#include "clk.h"
> +
> +
> +/* clocks in AO (always on) controller */
> +static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
> +   { HI6220_REF32K,"ref32k",   NULL, CLK_IS_ROOT, 32764, 
> },
> +   { HI6220_CLK_TCXO,  "clk_tcxo", NULL, CLK_IS_ROOT, 1920,  
> },
> +   { HI6220_MMC1_PAD,  "mmc1_pad", NULL, CLK_IS_ROOT, 1, 
> },
> +   { HI6220_MMC2_PAD,  "mmc2_pad", NULL, CLK_IS_ROOT, 1, 
> },
> +   { HI6220_MMC0_PAD,  "mmc0_pad", NULL, CLK_IS_ROOT, 2, 
> },
> +   { HI6220_PLL_BBP,   "bbppll0",  NULL, CLK_IS_ROOT, 24576, 
> },
> +   {

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-06-03 Thread Bintian 

On 2015/6/4 6:39, Michael Turquette wrote:

Quoting Bintian Wang (2015-05-28 19:08:38)

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
Tested-by: Kevin Hilman khil...@linaro.org


I've applied patches #4-6 to the clk tree.


Thank you Mike.

Best Regards,

Bintian


Regards,
Mike


---
  drivers/clk/Kconfig   |   1 +
  drivers/clk/Makefile  |   4 +-
  drivers/clk/hisilicon/Kconfig |   6 +
  drivers/clk/hisilicon/Makefile|   3 +-
  drivers/clk/hisilicon/clk-hi6220.c| 284 ++
  drivers/clk/hisilicon/clk.c   |  29 +++
  drivers/clk/hisilicon/clk.h   |  17 ++
  drivers/clk/hisilicon/clkdivider-hi6220.c | 156 
  8 files changed, 496 insertions(+), 4 deletions(-)
  create mode 100644 drivers/clk/hisilicon/Kconfig
  create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
  create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
   This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.

  source drivers/clk/bcm/Kconfig
+source drivers/clk/hisilicon/Kconfig
  source drivers/clk/qcom/Kconfig

  endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)  += clk-pwm.o
  obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
  obj-$(CONFIG_ARCH_BCM_MOBILE)  += bcm/
  obj-$(CONFIG_ARCH_BERLIN)  += berlin/
-obj-$(CONFIG_ARCH_HI3xxx)  += hisilicon/
-obj-$(CONFIG_ARCH_HIP04)   += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
  obj-$(CONFIG_ARCH_MXC) += imx/
  obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
  obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+   bool Hi6220 Clock Driver
+   depends on ARCH_HISI || COMPILE_TEST
+   default ARCH_HISI
+   help
+ Build the Hisilicon Hi6220 clock driver based on the common clock 
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
  # Hisilicon Clock specific Makefile
  #

-obj-y  += clk.o clkgate-separated.o
+obj-y  += clk.o clkgate-separated.o clkdivider-hi6220.o

  obj-$(CONFIG_ARCH_HI3xxx)  += clk-hi3620.o
  obj-$(CONFIG_ARCH_HIP04)   += clk-hip04.o
  obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+   { HI6220_REF32K,ref32k,   NULL, CLK_IS_ROOT, 32764, },
+   { HI6220_CLK_TCXO,  clk_tcxo, NULL, CLK_IS_ROOT, 1920,  },
+   { HI6220_MMC1_PAD,  mmc1_pad, NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC2_PAD,  mmc2_pad, NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC0_PAD,

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-06-03 Thread Michael Turquette 
Quoting Bintian Wang (2015-05-28 19:08:38)
 Add clock drivers for hi6220 SoC, this driver controls the SoC
 registers to supply different clocks to different IPs in the SoC.
 
 We add one divider clock for hi6220 because the divider in hi6220
 also has a mask bit but it doesnot obey the rule defined by flag
 CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
 left shift fixed bits (e.g. 16 bits), so we add this divider clock
 to handle it.
 
 Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
 Signed-off-by: Bintian Wang bintian.w...@huawei.com
 Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
 Reviewed-by: Zhangfei Gao zhangfei@linaro.org
 Tested-by: Will Deacon will.dea...@arm.com
 Tested-by: Tyler Baker tyler.ba...@linaro.org
 Tested-by: Kevin Hilman khil...@linaro.org

I've applied patches #4-6 to the clk tree.

Regards,
Mike

 ---
  drivers/clk/Kconfig   |   1 +
  drivers/clk/Makefile  |   4 +-
  drivers/clk/hisilicon/Kconfig |   6 +
  drivers/clk/hisilicon/Makefile|   3 +-
  drivers/clk/hisilicon/clk-hi6220.c| 284 
 ++
  drivers/clk/hisilicon/clk.c   |  29 +++
  drivers/clk/hisilicon/clk.h   |  17 ++
  drivers/clk/hisilicon/clkdivider-hi6220.c | 156 
  8 files changed, 496 insertions(+), 4 deletions(-)
  create mode 100644 drivers/clk/hisilicon/Kconfig
  create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
  create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
 
 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
 index de8c58f..cd6029d4 100644
 --- a/drivers/clk/Kconfig
 +++ b/drivers/clk/Kconfig
 @@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
   This driver supports TI CDCE706 programmable 3-PLL clock 
 synthesizer.
  
  source drivers/clk/bcm/Kconfig
 +source drivers/clk/hisilicon/Kconfig
  source drivers/clk/qcom/Kconfig
  
  endmenu
 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
 index d2d5e6c..440ef72 100644
 --- a/drivers/clk/Makefile
 +++ b/drivers/clk/Makefile
 @@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)  += clk-pwm.o
  obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
  obj-$(CONFIG_ARCH_BCM_MOBILE)  += bcm/
  obj-$(CONFIG_ARCH_BERLIN)  += berlin/
 -obj-$(CONFIG_ARCH_HI3xxx)  += hisilicon/
 -obj-$(CONFIG_ARCH_HIP04)   += hisilicon/
 -obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
 +obj-$(CONFIG_ARCH_HISI)+= hisilicon/
  obj-$(CONFIG_ARCH_MXC) += imx/
  obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
  obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
 diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
 new file mode 100644
 index 000..b4165ba
 --- /dev/null
 +++ b/drivers/clk/hisilicon/Kconfig
 @@ -0,0 +1,6 @@
 +config COMMON_CLK_HI6220
 +   bool Hi6220 Clock Driver
 +   depends on ARCH_HISI || COMPILE_TEST
 +   default ARCH_HISI
 +   help
 + Build the Hisilicon Hi6220 clock driver based on the common clock 
 framework.
 diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
 index 038c02f..48f0116 100644
 --- a/drivers/clk/hisilicon/Makefile
 +++ b/drivers/clk/hisilicon/Makefile
 @@ -2,8 +2,9 @@
  # Hisilicon Clock specific Makefile
  #
  
 -obj-y  += clk.o clkgate-separated.o
 +obj-y  += clk.o clkgate-separated.o clkdivider-hi6220.o
  
  obj-$(CONFIG_ARCH_HI3xxx)  += clk-hi3620.o
  obj-$(CONFIG_ARCH_HIP04)   += clk-hip04.o
  obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
 +obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
 diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
 b/drivers/clk/hisilicon/clk-hi6220.c
 new file mode 100644
 index 000..4563343
 --- /dev/null
 +++ b/drivers/clk/hisilicon/clk-hi6220.c
 @@ -0,0 +1,284 @@
 +/*
 + * Hisilicon Hi6220 clock driver
 + *
 + * Copyright (c) 2015 Hisilicon Limited.
 + *
 + * Author: Bintian Wang bintian.w...@huawei.com
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License version 2 as
 + * published by the Free Software Foundation.
 + */
 +
 +#include linux/kernel.h
 +#include linux/clk-provider.h
 +#include linux/clkdev.h
 +#include linux/io.h
 +#include linux/of.h
 +#include linux/of_address.h
 +#include linux/of_device.h
 +#include linux/slab.h
 +
 +#include dt-bindings/clock/hi6220-clock.h
 +
 +#include clk.h
 +
 +
 +/* clocks in AO (always on) controller */
 +static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
 +   { HI6220_REF32K,ref32k,   NULL, CLK_IS_ROOT, 32764, 
 },
 +   { HI6220_CLK_TCXO,  clk_tcxo, NULL, CLK_IS_ROOT, 1920,  
 },
 +   { HI6220_MMC1_PAD,  mmc1_pad, NULL, CLK_IS_ROOT, 1, 
 },
 +   { HI6220_MMC2_PAD,  mmc2_pad, NULL, CLK_IS_ROOT, 1, 
 },
 +

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Bintian 

Hello Mike,

On 2015/5/29 9:07, Michael Turquette wrote:

Quoting Kevin Hilman (2015-05-28 10:32:05)

Bintian  writes:


Hello Mike,

On 2015/5/28 13:26, Michael Turquette wrote:

Quoting Bintian Wang (2015-05-23 21:11:11)

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz 
Signed-off-by: Bintian Wang 
Acked-by: Haojian Zhuang 
Reviewed-by: Zhangfei Gao 
Tested-by: Will Deacon 
Tested-by: Tyler Baker 


Hi Bintian,

Thanks for making the changes requested by Stephen. I've taken his patch
to add assigned-clock-rate/parent support for AMBA interconnects and
applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
of that. You can find it at:

git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220

Thank you very much!

I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220:
Document devicetree bindings for hi6220 clock",  which described the
dt binding of clk, and it is also acked by Stephen(v4 is the same to
v5).


I have merged this into clk-next so it can get some cycles in
linux-next.

Stephen,

Can you send your patch out to Russell properly? It needs his ack (or
for him to take it outright) in order to unblock the hi6220 clock driver
from being merged.

It doesn't block hi6220 clock driver now, because the UART1 is not
enabled in hi6220 dts now.


Now that the clk changes are queued up, can you (re)post the remaining
hikey patches with a changelog stating the dependency on the clk-next
branch.  I believe what's left is just the DT and Kconfig/defconfig
changes, correct?


Just to be clear, clk-next-hi6220 is not an immutable branch. I just put
it up to get some testing done on it. Depending on whether or not
Russell acks Stephen's patch then it may be changed.

Stephen's patch can help UART1 to switch to the higher clock, so we can
remove the "clk_set_parent" from the "clk-hi6220.c" safely and don't
need to do that workaround in advance.

You know, we don't enable the UART1 in this series, and we can submit
other patch to enable it after Stephen's patch is merged.

Thanks,

Bintian



Regards,
Mike



With some acks from the DT maintainers, these should be ready to be
merged through arm-soc.

Thanks,

Kevin


.



--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Bintian Wang 
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz 
Signed-off-by: Bintian Wang 
Acked-by: Haojian Zhuang 
Reviewed-by: Zhangfei Gao 
Tested-by: Will Deacon 
Tested-by: Tyler Baker 
Tested-by: Kevin Hilman 
---
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   4 +-
 drivers/clk/hisilicon/Kconfig |   6 +
 drivers/clk/hisilicon/Makefile|   3 +-
 drivers/clk/hisilicon/clk-hi6220.c| 284 ++
 drivers/clk/hisilicon/clk.c   |  29 +++
 drivers/clk/hisilicon/clk.h   |  17 ++
 drivers/clk/hisilicon/clkdivider-hi6220.c | 156 
 8 files changed, 496 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/hisilicon/Kconfig
 create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
 create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
 
 source "drivers/clk/bcm/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/qcom/Kconfig"
 
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)  += clk-pwm.o
 obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
 obj-$(CONFIG_ARCH_BCM_MOBILE)  += bcm/
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
-obj-$(CONFIG_ARCH_HI3xxx)  += hisilicon/
-obj-$(CONFIG_ARCH_HIP04)   += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
 obj-$(CONFIG_ARCH_MXC) += imx/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+   bool "Hi6220 Clock Driver"
+   depends on ARCH_HISI || COMPILE_TEST
+   default ARCH_HISI
+   help
+ Build the Hisilicon Hi6220 clock driver based on the common clock 
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
 # Hisilicon Clock specific Makefile
 #
 
-obj-y  += clk.o clkgate-separated.o
+obj-y  += clk.o clkgate-separated.o clkdivider-hi6220.o
 
 obj-$(CONFIG_ARCH_HI3xxx)  += clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)   += clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+   { HI6220_REF32K,"ref32k",   NULL, CLK_IS_ROOT, 32764, },
+   { HI6220_CLK_TCXO,  "clk_tcxo", NULL, CLK_IS_ROOT, 1920,  },
+   { HI6220_MMC1_PAD,  "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC2_PAD,  "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC0_PAD,  "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+   { HI6220_PLL_BBP,   "bbppll0",  NULL, CLK_IS_ROOT, 24576, },
+   { HI6220_PLL_GPU,   "gpupll",   NULL, CLK_IS_ROOT, 10,},
+   { HI6220_PLL1_DDR,  "ddrpll1",  NULL, CLK_IS_ROOT, 106600,},
+   { HI6220_PLL_SYS,   "syspll",   NULL, CLK_IS_ROOT, 12,},
+   { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 12,},
+   { HI6220_DDR_SRC,   "ddr_sel_src",  NULL, CLK_IS_ROOT,

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Michael Turquette 
Quoting Kevin Hilman (2015-05-28 10:32:05)
> Bintian  writes:
> 
> > Hello Mike,
> >
> > On 2015/5/28 13:26, Michael Turquette wrote:
> >> Quoting Bintian Wang (2015-05-23 21:11:11)
> >>> Add clock drivers for hi6220 SoC, this driver controls the SoC
> >>> registers to supply different clocks to different IPs in the SoC.
> >>>
> >>> We add one divider clock for hi6220 because the divider in hi6220
> >>> also has a mask bit but it doesnot obey the rule defined by flag
> >>> "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
> >>> left shift fixed bits (e.g. 16 bits), so we add this divider clock
> >>> to handle it.
> >>>
> >>> Signed-off-by: Jorge Ramirez-Ortiz 
> >>> Signed-off-by: Bintian Wang 
> >>> Acked-by: Haojian Zhuang 
> >>> Reviewed-by: Zhangfei Gao 
> >>> Tested-by: Will Deacon 
> >>> Tested-by: Tyler Baker 
> >>
> >> Hi Bintian,
> >>
> >> Thanks for making the changes requested by Stephen. I've taken his patch
> >> to add assigned-clock-rate/parent support for AMBA interconnects and
> >> applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
> >> of that. You can find it at:
> >>
> >> git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220
> > Thank you very much!
> >
> > I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220:
> > Document devicetree bindings for hi6220 clock",  which described the
> > dt binding of clk, and it is also acked by Stephen(v4 is the same to
> > v5).
> >
> >> I have merged this into clk-next so it can get some cycles in
> >> linux-next.
> >>
> >> Stephen,
> >>
> >> Can you send your patch out to Russell properly? It needs his ack (or
> >> for him to take it outright) in order to unblock the hi6220 clock driver
> >> from being merged.
> > It doesn't block hi6220 clock driver now, because the UART1 is not
> > enabled in hi6220 dts now.
> 
> Now that the clk changes are queued up, can you (re)post the remaining
> hikey patches with a changelog stating the dependency on the clk-next
> branch.  I believe what's left is just the DT and Kconfig/defconfig
> changes, correct?

Just to be clear, clk-next-hi6220 is not an immutable branch. I just put
it up to get some testing done on it. Depending on whether or not
Russell acks Stephen's patch then it may be changed.

Regards,
Mike

> 
> With some acks from the DT maintainers, these should be ready to be
> merged through arm-soc.
> 
> Thanks,
> 
> Kevin
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Bintian 

Hello Kevin,

On 2015/5/29 1:32, Kevin Hilman wrote:

Bintian  writes:


Hello Mike,

On 2015/5/28 13:26, Michael Turquette wrote:

Quoting Bintian Wang (2015-05-23 21:11:11)

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz 
Signed-off-by: Bintian Wang 
Acked-by: Haojian Zhuang 
Reviewed-by: Zhangfei Gao 
Tested-by: Will Deacon 
Tested-by: Tyler Baker 


Hi Bintian,

Thanks for making the changes requested by Stephen. I've taken his patch
to add assigned-clock-rate/parent support for AMBA interconnects and
applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
of that. You can find it at:

git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220

Thank you very much!

I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220:
Document devicetree bindings for hi6220 clock",  which described the
dt binding of clk, and it is also acked by Stephen(v4 is the same to
v5).


I have merged this into clk-next so it can get some cycles in
linux-next.

Stephen,

Can you send your patch out to Russell properly? It needs his ack (or
for him to take it outright) in order to unblock the hi6220 clock driver
from being merged.

It doesn't block hi6220 clock driver now, because the UART1 is not
enabled in hi6220 dts now.


Now that the clk changes are queued up, can you (re)post the remaining
hikey patches with a changelog stating the dependency on the clk-next
branch.  I believe what's left is just the DT and Kconfig/defconfig
changes, correct?

Yes, you are right.

I will post the remaining hikey patches soon.

Thank you Kevin,

BR,

Bintian


With some acks from the DT maintainers, these should be ready to be
merged through arm-soc.

Thanks,

Kevin

.



--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Kevin Hilman 
Bintian  writes:

> Hello Mike,
>
> On 2015/5/28 13:26, Michael Turquette wrote:
>> Quoting Bintian Wang (2015-05-23 21:11:11)
>>> Add clock drivers for hi6220 SoC, this driver controls the SoC
>>> registers to supply different clocks to different IPs in the SoC.
>>>
>>> We add one divider clock for hi6220 because the divider in hi6220
>>> also has a mask bit but it doesnot obey the rule defined by flag
>>> "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
>>> left shift fixed bits (e.g. 16 bits), so we add this divider clock
>>> to handle it.
>>>
>>> Signed-off-by: Jorge Ramirez-Ortiz 
>>> Signed-off-by: Bintian Wang 
>>> Acked-by: Haojian Zhuang 
>>> Reviewed-by: Zhangfei Gao 
>>> Tested-by: Will Deacon 
>>> Tested-by: Tyler Baker 
>>
>> Hi Bintian,
>>
>> Thanks for making the changes requested by Stephen. I've taken his patch
>> to add assigned-clock-rate/parent support for AMBA interconnects and
>> applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
>> of that. You can find it at:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220
> Thank you very much!
>
> I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220:
> Document devicetree bindings for hi6220 clock",  which described the
> dt binding of clk, and it is also acked by Stephen(v4 is the same to
> v5).
>
>> I have merged this into clk-next so it can get some cycles in
>> linux-next.
>>
>> Stephen,
>>
>> Can you send your patch out to Russell properly? It needs his ack (or
>> for him to take it outright) in order to unblock the hi6220 clock driver
>> from being merged.
> It doesn't block hi6220 clock driver now, because the UART1 is not
> enabled in hi6220 dts now.

Now that the clk changes are queued up, can you (re)post the remaining
hikey patches with a changelog stating the dependency on the clk-next
branch.  I believe what's left is just the DT and Kconfig/defconfig
changes, correct?

With some acks from the DT maintainers, these should be ready to be
merged through arm-soc.

Thanks,

Kevin
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Bintian 

Hello Mike,

On 2015/5/28 13:26, Michael Turquette wrote:

Quoting Bintian Wang (2015-05-23 21:11:11)

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz 
Signed-off-by: Bintian Wang 
Acked-by: Haojian Zhuang 
Reviewed-by: Zhangfei Gao 
Tested-by: Will Deacon 
Tested-by: Tyler Baker 


Hi Bintian,

Thanks for making the changes requested by Stephen. I've taken his patch
to add assigned-clock-rate/parent support for AMBA interconnects and
applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
of that. You can find it at:

git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220

Thank you very much!

I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220: 
Document devicetree bindings for hi6220 clock",  which described the dt 
binding of clk, and it is also acked by Stephen(v4 is the same to v5).



I have merged this into clk-next so it can get some cycles in
linux-next.

Stephen,

Can you send your patch out to Russell properly? It needs his ack (or
for him to take it outright) in order to unblock the hi6220 clock driver
from being merged.

It doesn't block hi6220 clock driver now, because the UART1 is not
enabled in hi6220 dts now.

Thanks!

Bintian


Regards,
Mike

.



--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Kevin Hilman 
Bintian bintian.w...@huawei.com writes:

 Hello Mike,

 On 2015/5/28 13:26, Michael Turquette wrote:
 Quoting Bintian Wang (2015-05-23 21:11:11)
 Add clock drivers for hi6220 SoC, this driver controls the SoC
 registers to supply different clocks to different IPs in the SoC.

 We add one divider clock for hi6220 because the divider in hi6220
 also has a mask bit but it doesnot obey the rule defined by flag
 CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
 left shift fixed bits (e.g. 16 bits), so we add this divider clock
 to handle it.

 Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
 Signed-off-by: Bintian Wang bintian.w...@huawei.com
 Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
 Reviewed-by: Zhangfei Gao zhangfei@linaro.org
 Tested-by: Will Deacon will.dea...@arm.com
 Tested-by: Tyler Baker tyler.ba...@linaro.org

 Hi Bintian,

 Thanks for making the changes requested by Stephen. I've taken his patch
 to add assigned-clock-rate/parent support for AMBA interconnects and
 applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
 of that. You can find it at:

 git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220
 Thank you very much!

 I think you also need to pick patch [PATCH v5 3/6] clk: hi6220:
 Document devicetree bindings for hi6220 clock,  which described the
 dt binding of clk, and it is also acked by Stephen(v4 is the same to
 v5).

 I have merged this into clk-next so it can get some cycles in
 linux-next.

 Stephen,

 Can you send your patch out to Russell properly? It needs his ack (or
 for him to take it outright) in order to unblock the hi6220 clock driver
 from being merged.
 It doesn't block hi6220 clock driver now, because the UART1 is not
 enabled in hi6220 dts now.

Now that the clk changes are queued up, can you (re)post the remaining
hikey patches with a changelog stating the dependency on the clk-next
branch.  I believe what's left is just the DT and Kconfig/defconfig
changes, correct?

With some acks from the DT maintainers, these should be ready to be
merged through arm-soc.

Thanks,

Kevin
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Bintian 

Hello Kevin,

On 2015/5/29 1:32, Kevin Hilman wrote:

Bintian bintian.w...@huawei.com writes:


Hello Mike,

On 2015/5/28 13:26, Michael Turquette wrote:

Quoting Bintian Wang (2015-05-23 21:11:11)

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org


Hi Bintian,

Thanks for making the changes requested by Stephen. I've taken his patch
to add assigned-clock-rate/parent support for AMBA interconnects and
applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
of that. You can find it at:

git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220

Thank you very much!

I think you also need to pick patch [PATCH v5 3/6] clk: hi6220:
Document devicetree bindings for hi6220 clock,  which described the
dt binding of clk, and it is also acked by Stephen(v4 is the same to
v5).


I have merged this into clk-next so it can get some cycles in
linux-next.

Stephen,

Can you send your patch out to Russell properly? It needs his ack (or
for him to take it outright) in order to unblock the hi6220 clock driver
from being merged.

It doesn't block hi6220 clock driver now, because the UART1 is not
enabled in hi6220 dts now.


Now that the clk changes are queued up, can you (re)post the remaining
hikey patches with a changelog stating the dependency on the clk-next
branch.  I believe what's left is just the DT and Kconfig/defconfig
changes, correct?

Yes, you are right.

I will post the remaining hikey patches soon.

Thank you Kevin,

BR,

Bintian


With some acks from the DT maintainers, these should be ready to be
merged through arm-soc.

Thanks,

Kevin

.



--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Bintian Wang 
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
Tested-by: Kevin Hilman khil...@linaro.org
---
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   4 +-
 drivers/clk/hisilicon/Kconfig |   6 +
 drivers/clk/hisilicon/Makefile|   3 +-
 drivers/clk/hisilicon/clk-hi6220.c| 284 ++
 drivers/clk/hisilicon/clk.c   |  29 +++
 drivers/clk/hisilicon/clk.h   |  17 ++
 drivers/clk/hisilicon/clkdivider-hi6220.c | 156 
 8 files changed, 496 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/hisilicon/Kconfig
 create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
 create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
 
 source drivers/clk/bcm/Kconfig
+source drivers/clk/hisilicon/Kconfig
 source drivers/clk/qcom/Kconfig
 
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)  += clk-pwm.o
 obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
 obj-$(CONFIG_ARCH_BCM_MOBILE)  += bcm/
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
-obj-$(CONFIG_ARCH_HI3xxx)  += hisilicon/
-obj-$(CONFIG_ARCH_HIP04)   += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
 obj-$(CONFIG_ARCH_MXC) += imx/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+   bool Hi6220 Clock Driver
+   depends on ARCH_HISI || COMPILE_TEST
+   default ARCH_HISI
+   help
+ Build the Hisilicon Hi6220 clock driver based on the common clock 
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
 # Hisilicon Clock specific Makefile
 #
 
-obj-y  += clk.o clkgate-separated.o
+obj-y  += clk.o clkgate-separated.o clkdivider-hi6220.o
 
 obj-$(CONFIG_ARCH_HI3xxx)  += clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)   += clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+   { HI6220_REF32K,ref32k,   NULL, CLK_IS_ROOT, 32764, },
+   { HI6220_CLK_TCXO,  clk_tcxo, NULL, CLK_IS_ROOT, 1920,  },
+   { HI6220_MMC1_PAD,  mmc1_pad, NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC2_PAD,  mmc2_pad, NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC0_PAD,  mmc0_pad, NULL, CLK_IS_ROOT, 2, },
+   { HI6220_PLL_BBP,   bbppll0,  NULL, CLK_IS_ROOT, 24576, },
+   { HI6220_PLL_GPU,   gpupll,   NULL, CLK_IS_ROOT, 10,},
+

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Bintian 

Hello Mike,

On 2015/5/29 9:07, Michael Turquette wrote:

Quoting Kevin Hilman (2015-05-28 10:32:05)

Bintian bintian.w...@huawei.com writes:


Hello Mike,

On 2015/5/28 13:26, Michael Turquette wrote:

Quoting Bintian Wang (2015-05-23 21:11:11)

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org


Hi Bintian,

Thanks for making the changes requested by Stephen. I've taken his patch
to add assigned-clock-rate/parent support for AMBA interconnects and
applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
of that. You can find it at:

git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220

Thank you very much!

I think you also need to pick patch [PATCH v5 3/6] clk: hi6220:
Document devicetree bindings for hi6220 clock,  which described the
dt binding of clk, and it is also acked by Stephen(v4 is the same to
v5).


I have merged this into clk-next so it can get some cycles in
linux-next.

Stephen,

Can you send your patch out to Russell properly? It needs his ack (or
for him to take it outright) in order to unblock the hi6220 clock driver
from being merged.

It doesn't block hi6220 clock driver now, because the UART1 is not
enabled in hi6220 dts now.


Now that the clk changes are queued up, can you (re)post the remaining
hikey patches with a changelog stating the dependency on the clk-next
branch.  I believe what's left is just the DT and Kconfig/defconfig
changes, correct?


Just to be clear, clk-next-hi6220 is not an immutable branch. I just put
it up to get some testing done on it. Depending on whether or not
Russell acks Stephen's patch then it may be changed.

Stephen's patch can help UART1 to switch to the higher clock, so we can
remove the clk_set_parent from the clk-hi6220.c safely and don't
need to do that workaround in advance.

You know, we don't enable the UART1 in this series, and we can submit
other patch to enable it after Stephen's patch is merged.

Thanks,

Bintian



Regards,
Mike



With some acks from the DT maintainers, these should be ready to be
merged through arm-soc.

Thanks,

Kevin


.



--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Michael Turquette 
Quoting Kevin Hilman (2015-05-28 10:32:05)
 Bintian bintian.w...@huawei.com writes:
 
  Hello Mike,
 
  On 2015/5/28 13:26, Michael Turquette wrote:
  Quoting Bintian Wang (2015-05-23 21:11:11)
  Add clock drivers for hi6220 SoC, this driver controls the SoC
  registers to supply different clocks to different IPs in the SoC.
 
  We add one divider clock for hi6220 because the divider in hi6220
  also has a mask bit but it doesnot obey the rule defined by flag
  CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
  left shift fixed bits (e.g. 16 bits), so we add this divider clock
  to handle it.
 
  Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
  Signed-off-by: Bintian Wang bintian.w...@huawei.com
  Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
  Reviewed-by: Zhangfei Gao zhangfei@linaro.org
  Tested-by: Will Deacon will.dea...@arm.com
  Tested-by: Tyler Baker tyler.ba...@linaro.org
 
  Hi Bintian,
 
  Thanks for making the changes requested by Stephen. I've taken his patch
  to add assigned-clock-rate/parent support for AMBA interconnects and
  applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
  of that. You can find it at:
 
  git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220
  Thank you very much!
 
  I think you also need to pick patch [PATCH v5 3/6] clk: hi6220:
  Document devicetree bindings for hi6220 clock,  which described the
  dt binding of clk, and it is also acked by Stephen(v4 is the same to
  v5).
 
  I have merged this into clk-next so it can get some cycles in
  linux-next.
 
  Stephen,
 
  Can you send your patch out to Russell properly? It needs his ack (or
  for him to take it outright) in order to unblock the hi6220 clock driver
  from being merged.
  It doesn't block hi6220 clock driver now, because the UART1 is not
  enabled in hi6220 dts now.
 
 Now that the clk changes are queued up, can you (re)post the remaining
 hikey patches with a changelog stating the dependency on the clk-next
 branch.  I believe what's left is just the DT and Kconfig/defconfig
 changes, correct?

Just to be clear, clk-next-hi6220 is not an immutable branch. I just put
it up to get some testing done on it. Depending on whether or not
Russell acks Stephen's patch then it may be changed.

Regards,
Mike

 
 With some acks from the DT maintainers, these should be ready to be
 merged through arm-soc.
 
 Thanks,
 
 Kevin
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-28 Thread Bintian 

Hello Mike,

On 2015/5/28 13:26, Michael Turquette wrote:

Quoting Bintian Wang (2015-05-23 21:11:11)

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org


Hi Bintian,

Thanks for making the changes requested by Stephen. I've taken his patch
to add assigned-clock-rate/parent support for AMBA interconnects and
applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
of that. You can find it at:

git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220

Thank you very much!

I think you also need to pick patch [PATCH v5 3/6] clk: hi6220: 
Document devicetree bindings for hi6220 clock,  which described the dt 
binding of clk, and it is also acked by Stephen(v4 is the same to v5).



I have merged this into clk-next so it can get some cycles in
linux-next.

Stephen,

Can you send your patch out to Russell properly? It needs his ack (or
for him to take it outright) in order to unblock the hi6220 clock driver
from being merged.

It doesn't block hi6220 clock driver now, because the UART1 is not
enabled in hi6220 dts now.

Thanks!

Bintian


Regards,
Mike

.



--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-27 Thread Michael Turquette 
Quoting Bintian Wang (2015-05-23 21:11:11)
> Add clock drivers for hi6220 SoC, this driver controls the SoC
> registers to supply different clocks to different IPs in the SoC.
> 
> We add one divider clock for hi6220 because the divider in hi6220
> also has a mask bit but it doesnot obey the rule defined by flag
> "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
> left shift fixed bits (e.g. 16 bits), so we add this divider clock
> to handle it.
> 
> Signed-off-by: Jorge Ramirez-Ortiz 
> Signed-off-by: Bintian Wang 
> Acked-by: Haojian Zhuang 
> Reviewed-by: Zhangfei Gao 
> Tested-by: Will Deacon 
> Tested-by: Tyler Baker 

Hi Bintian,

Thanks for making the changes requested by Stephen. I've taken his patch
to add assigned-clock-rate/parent support for AMBA interconnects and
applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
of that. You can find it at:

git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220

I have merged this into clk-next so it can get some cycles in
linux-next.

Stephen,

Can you send your patch out to Russell properly? It needs his ack (or
for him to take it outright) in order to unblock the hi6220 clock driver
from being merged.

Regards,
Mike
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-27 Thread Michael Turquette 
Quoting Bintian Wang (2015-05-23 21:11:11)
 Add clock drivers for hi6220 SoC, this driver controls the SoC
 registers to supply different clocks to different IPs in the SoC.
 
 We add one divider clock for hi6220 because the divider in hi6220
 also has a mask bit but it doesnot obey the rule defined by flag
 CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
 left shift fixed bits (e.g. 16 bits), so we add this divider clock
 to handle it.
 
 Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
 Signed-off-by: Bintian Wang bintian.w...@huawei.com
 Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
 Reviewed-by: Zhangfei Gao zhangfei@linaro.org
 Tested-by: Will Deacon will.dea...@arm.com
 Tested-by: Tyler Baker tyler.ba...@linaro.org

Hi Bintian,

Thanks for making the changes requested by Stephen. I've taken his patch
to add assigned-clock-rate/parent support for AMBA interconnects and
applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top
of that. You can find it at:

git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220

I have merged this into clk-next so it can get some cycles in
linux-next.

Stephen,

Can you send your patch out to Russell properly? It needs his ack (or
for him to take it outright) in order to unblock the hi6220 clock driver
from being merged.

Regards,
Mike
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-23 Thread Bintian Wang 
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz 
Signed-off-by: Bintian Wang 
Acked-by: Haojian Zhuang 
Reviewed-by: Zhangfei Gao 
Tested-by: Will Deacon 
Tested-by: Tyler Baker 
---
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   4 +-
 drivers/clk/hisilicon/Kconfig |   6 +
 drivers/clk/hisilicon/Makefile|   3 +-
 drivers/clk/hisilicon/clk-hi6220.c| 284 ++
 drivers/clk/hisilicon/clk.c   |  29 +++
 drivers/clk/hisilicon/clk.h   |  17 ++
 drivers/clk/hisilicon/clkdivider-hi6220.c | 156 
 8 files changed, 496 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/hisilicon/Kconfig
 create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
 create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
 
 source "drivers/clk/bcm/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/qcom/Kconfig"
 
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)  += clk-pwm.o
 obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
 obj-$(CONFIG_ARCH_BCM_MOBILE)  += bcm/
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
-obj-$(CONFIG_ARCH_HI3xxx)  += hisilicon/
-obj-$(CONFIG_ARCH_HIP04)   += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
 obj-$(CONFIG_ARCH_MXC) += imx/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+   bool "Hi6220 Clock Driver"
+   depends on ARCH_HISI || COMPILE_TEST
+   default ARCH_HISI
+   help
+ Build the Hisilicon Hi6220 clock driver based on the common clock 
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
 # Hisilicon Clock specific Makefile
 #
 
-obj-y  += clk.o clkgate-separated.o
+obj-y  += clk.o clkgate-separated.o clkdivider-hi6220.o
 
 obj-$(CONFIG_ARCH_HI3xxx)  += clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)   += clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+   { HI6220_REF32K,"ref32k",   NULL, CLK_IS_ROOT, 32764, },
+   { HI6220_CLK_TCXO,  "clk_tcxo", NULL, CLK_IS_ROOT, 1920,  },
+   { HI6220_MMC1_PAD,  "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC2_PAD,  "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC0_PAD,  "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+   { HI6220_PLL_BBP,   "bbppll0",  NULL, CLK_IS_ROOT, 24576, },
+   { HI6220_PLL_GPU,   "gpupll",   NULL, CLK_IS_ROOT, 10,},
+   { HI6220_PLL1_DDR,  "ddrpll1",  NULL, CLK_IS_ROOT, 106600,},
+   { HI6220_PLL_SYS,   "syspll",   NULL, CLK_IS_ROOT, 12,},
+   { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, CLK_IS_ROOT, 12,},
+   { HI6220_DDR_SRC,   "ddr_sel_src",  NULL, CLK_IS_ROOT, 12,},
+   {

[PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

2015-05-23 Thread Bintian Wang 
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
---
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   4 +-
 drivers/clk/hisilicon/Kconfig |   6 +
 drivers/clk/hisilicon/Makefile|   3 +-
 drivers/clk/hisilicon/clk-hi6220.c| 284 ++
 drivers/clk/hisilicon/clk.c   |  29 +++
 drivers/clk/hisilicon/clk.h   |  17 ++
 drivers/clk/hisilicon/clkdivider-hi6220.c | 156 
 8 files changed, 496 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/hisilicon/Kconfig
 create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
 create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
 
 source drivers/clk/bcm/Kconfig
+source drivers/clk/hisilicon/Kconfig
 source drivers/clk/qcom/Kconfig
 
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM)  += clk-pwm.o
 obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
 obj-$(CONFIG_ARCH_BCM_MOBILE)  += bcm/
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
-obj-$(CONFIG_ARCH_HI3xxx)  += hisilicon/
-obj-$(CONFIG_ARCH_HIP04)   += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
 obj-$(CONFIG_ARCH_MXC) += imx/
 obj-$(CONFIG_COMMON_CLK_KEYSTONE)  += keystone/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+   bool Hi6220 Clock Driver
+   depends on ARCH_HISI || COMPILE_TEST
+   default ARCH_HISI
+   help
+ Build the Hisilicon Hi6220 clock driver based on the common clock 
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
 # Hisilicon Clock specific Makefile
 #
 
-obj-y  += clk.o clkgate-separated.o
+obj-y  += clk.o clkgate-separated.o clkdivider-hi6220.o
 
 obj-$(CONFIG_ARCH_HI3xxx)  += clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)   += clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+   { HI6220_REF32K,ref32k,   NULL, CLK_IS_ROOT, 32764, },
+   { HI6220_CLK_TCXO,  clk_tcxo, NULL, CLK_IS_ROOT, 1920,  },
+   { HI6220_MMC1_PAD,  mmc1_pad, NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC2_PAD,  mmc2_pad, NULL, CLK_IS_ROOT, 1, },
+   { HI6220_MMC0_PAD,  mmc0_pad, NULL, CLK_IS_ROOT, 2, },
+   { HI6220_PLL_BBP,   bbppll0,  NULL, CLK_IS_ROOT, 24576, },
+   { HI6220_PLL_GPU,   gpupll,   NULL, CLK_IS_ROOT, 10,},
+   { HI6220_PLL1_DDR,  ddrpll1,