Re: [PATCH v9] ARM: clocksource: add support for MOXA ART SoCs

[Daniel Lezcano]

On 07/20/2013 10:45 PM, Linus Walleij wrote:
> On Wed, Jul 17, 2013 at 10:04 AM, Jonas Jensen  wrote:
> 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
> 
> #include 
> 
>> +#define TIMEREG_CR_1_ENABLEBIT(0)
> 
> Because BIT() comes from there. And we shall not rely on
> implicit #inclusion.

Hi Jonas,

as the patchset is already merged could you fix it with a separate patch ?

Thanks
  -- Daniel

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Re: [PATCH v9] ARM: clocksource: add support for MOXA ART SoCs

[Linus Walleij]

On Wed, Jul 17, 2013 at 10:04 AM, Jonas Jensen  wrote:

> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 

#include 

> +#define TIMEREG_CR_1_ENABLEBIT(0)

Because BIT() comes from there. And we shall not rely on
implicit #inclusion.

Apart from that:
Reviewed-by: Linus Walleij 

Yours,
Linus Walleij
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[PATCH v9] ARM: clocksource: add support for MOXA ART SoCs

[Jonas Jensen]

This patch adds an clocksource driver for the main timer(s)
found on MOXA ART SoCs.

The MOXA ART SoC provides three separate timers with individual
count/load/match registers, two are used here:

TIMER1: clockevents, used to support oneshot and periodic events
TIMER2: set up as a free running counter, used as clocksource

Timers are preconfigured by bootloader to count down and interrupt
on match or zero. Count increments every APB clock cycle and is
automatically reloaded when it reaches zero.

Signed-off-by: Jonas Jensen 
---

Notes:
Changes since v8:

1. add devicetree bindings document

Applies to next-20130716

 .../bindings/timer/moxa,moxart-timer.txt   |  17 +++
 drivers/clocksource/Makefile   |   1 +
 drivers/clocksource/moxart_timer.c | 164 +
 3 files changed, 182 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
 create mode 100644 drivers/clocksource/moxart_timer.c

diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt 
b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
new file mode 100644
index 000..77c4cfa
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
@@ -0,0 +1,17 @@
+MOXA ART timer
+
+Required properties:
+
+- compatible : Should be "moxa,moxart-timer"
+- reg : Should contain registers location and length
+- interrupts : Should contain the timer interrupt number
+- clocks : Should contain phandle for APB clock "clkapb"
+
+Example:
+
+   timer: timer@9840 {
+   compatible = "moxa,moxart-timer";
+   reg = <0x9840 0x42>;
+   interrupts = <19 1>;
+   clocks = <&clkapb>;
+   };
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8b00c5c..704d6d3 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
 obj-$(CONFIG_ORION_TIMER)  += time-orion.o
 obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
 obj-$(CONFIG_ARCH_MARCO)   += timer-marco.o
+obj-$(CONFIG_ARCH_MOXART)  += moxart_timer.o
 obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
 obj-$(CONFIG_ARCH_PRIMA2)  += timer-prima2.o
 obj-$(CONFIG_SUN4I_TIMER)  += sun4i_timer.o
diff --git a/drivers/clocksource/moxart_timer.c 
b/drivers/clocksource/moxart_timer.c
new file mode 100644
index 000..08a5943
--- /dev/null
+++ b/drivers/clocksource/moxart_timer.c
@@ -0,0 +1,164 @@
+/*
+ * MOXA ART SoCs timer handling.
+ *
+ * Copyright (C) 2013 Jonas Jensen
+ *
+ * Jonas Jensen 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define TIMER1_BASE0x00
+#define TIMER2_BASE0x10
+#define TIMER3_BASE0x20
+
+#define REG_COUNT  0x0 /* writable */
+#define REG_LOAD   0x4
+#define REG_MATCH1 0x8
+#define REG_MATCH2 0xC
+
+#define TIMER_CR   0x30
+#define TIMER_INTR_STATE   0x34
+#define TIMER_INTR_MASK0x38
+
+/*
+ * TIMER_CR flags:
+ *
+ * TIMEREG_CR_*_CLOCK  0: PCLK, 1: EXT1CLK
+ * TIMEREG_CR_*_INToverflow interrupt enable bit
+ */
+#define TIMEREG_CR_1_ENABLEBIT(0)
+#define TIMEREG_CR_1_CLOCK BIT(1)
+#define TIMEREG_CR_1_INT   BIT(2)
+#define TIMEREG_CR_2_ENABLEBIT(3)
+#define TIMEREG_CR_2_CLOCK BIT(4)
+#define TIMEREG_CR_2_INT   BIT(5)
+#define TIMEREG_CR_3_ENABLEBIT(6)
+#define TIMEREG_CR_3_CLOCK BIT(7)
+#define TIMEREG_CR_3_INT   BIT(8)
+#define TIMEREG_CR_COUNT_UPBIT(9)
+
+#define TIMER1_ENABLE  (TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE)
+#define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE)
+
+static void __iomem *base;
+static unsigned int clock_count_per_tick;
+
+static void moxart_clkevt_mode(enum clock_event_mode mode,
+  struct clock_event_device *clk)
+{
+   switch (mode) {
+   case CLOCK_EVT_MODE_RESUME:
+   case CLOCK_EVT_MODE_ONESHOT:
+   writel(TIMER1_DISABLE, base + TIMER_CR);
+   writel(~0, base + TIMER1_BASE + REG_LOAD);
+   break;
+   case CLOCK_EVT_MODE_PERIODIC:
+   writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
+   writel(TIMER1_ENABLE, base + TIMER_CR);
+   break;
+   case CLOCK_EVT_MODE_UNUSED:
+   case CLOCK_EVT_MODE_SHUTDOWN:
+   default:
+   writel(TIMER1_DISABLE, base + TIMER_CR);
+   break;
+   }
+}
+
+static int moxart_clkevt_next_event(unsigned long cycles,
+   struct clock_event_device *unused)
+{
+