RE: [PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash Controller

[Naga Sureshkumar Relli]

Hi Miquel,

Thanks for reviewing this patch series.

> -Original Message-
> From: Miquel RAYNAL [mailto:miquel.ray...@free-electrons.com]
> Sent: Friday, December 29, 2017 2:25 AM
> To: Naga Sureshkumar Relli <nagas...@xilinx.com>
> Cc: boris.brezil...@free-electrons.com; rich...@nod.at;
> computersforpe...@gmail.com; marek.va...@gmail.com;
> cyrille.pitc...@wedev4u.fr; Naga Sureshkumar Relli <nagas...@xilinx.com>;
> nagasures...@gmail.com; linux-kernel@vger.kernel.org; linux-
> m...@lists.infradead.org; Punnaiah Choudary Kalluri <punn...@xilinx.com>;
> Michal Simek <mich...@xilinx.com>; dw...@infradead.org
> Subject: Re: [PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash
> Controller
> 
> Hello,
> 
> Thanks for contributing this driver.
> 
> As you may know, the NAND framework is currently moving to an interface
> called ->exec_op(). Please look at the l2-mtd -or linux-next- tree to see 
> what this
> is (drivers/mtd/nand/nand_base.c is quite well documented about this
> interface).
> 
> New drivers should drop their ->cmdfunc() / ->cmd_ctrl() /
> ->read/write_byte/word/buf() implementations and instead switch to
> ->exec_op(). I know this is a significant amount of work but do not
> hesitate to ask if you need some help.

Ok I will update the driver as per new exec_op() update.
Let me go through this interface.
> 
> You may take the Marvell NAND controller driver as example of how to
> implement it (rework also currently under review):
> https://www.spinics.net/lists/arm-kernel/msg624246.html
Ok, I will take a look into that driver.

> 
> Otherwise there are some comments below. I am really not a NAND god, so
> don't take them as pure truth :)
Thanks for reviewing this driver. 
> 
> Thank you,
> Miquèl
> 
> On Thu, 14 Dec 2017 19:14:45 +0530
> Naga Sureshkumar Relli <naga.sureshkumar.re...@xilinx.com> wrote:
> 
> > Added the basic driver for Arasan NAND Flash Controller used in Zynq
> > UltraScale+ MPSoC. It supports only Hw ECC and upto 24bit correction.
> >
> > Signed-off-by: Naga Sureshkumar Relli <nagas...@xilinx.com>
> > Signed-off-by: Punnaiah Choudary Kalluri <punn...@xilinx.com>
> > ---
> > Changes in v9:
> >  - Added the SPDX tags
> > Changes in v8:
> >  - Implemented setup_data_interface hook
> >  - fixed checkpatch --strict warnings
> >  - Added anfc_config_ecc in read_page_hwecc
> >  - Fixed returning status value by reading flash status in read_byte()
> >instead of reading previous value.
> > Changes in v7:
> > - Implemented Marek suggestions and comments
> > - Corrected the acronyms those should be in caps
> > - Modified kconfig/Make file to keep arasan entry in sorted order
> > - Added is_vmlloc_addr check
> > - Used ioread/write32_rep variants to avoid compilation error for
> > intel platforms
> > - separated PIO and DMA mode read/write functions
> > - Minor cleanup
> > Chnages in v6:
> > - Addressed most of the Brian and Boris comments
> > - Separated the nandchip from the nand controller
> > - Removed the ecc lookup table from driver
> > - Now use framework nand waitfunction and readoob
> > - Fixed the compiler warning
> > - Adapted the new frameowrk changes related to ecc and ooblayout
> > - Disabled the clocks after the nand_reelase
> > - Now using only one completion object
> > - Boris suggessions like adapting cmd_ctrl and rework on read/write
> > byte are not implemented and i will patch them later
> > - Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr
> > will implement later once the basic driver is mainlined.
> > Changes in v5:
> > - Renamed the driver filei as arasan_nand.c
> > - Fixed all comments relaqted coding style
> > - Fixed comments related to propagating the errors
> > - Modified the anfc_write_page_hwecc as per the write_page
> >   prototype
> > Changes in v4:
> > - Added support for onfi timing mode configuration
> > - Added clock suort
> > - Added support for multiple chipselects Changes in v3:
> > - Removed unused variables
> > - Avoided busy loop and used jifies based implementation
> > - Fixed compiler warnings "right shift count >= width of type"
> > - Removed unneeded codei and improved error reporting
> > - Added onfi version check to ensure reading the valid address cycles
> > Changes in v2:
> > - Added missing of.h to avoid kbuild system report erro
> > ---
> >  drivers/mtd/nand/Kconfig   |8 +
> >  drivers/mtd/nand/Makefile  |1 +
> >  drivers/mtd/nand/arasan_

RE: [PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash Controller

[Naga Sureshkumar Relli]

Hi Miquel,

Thanks for reviewing this patch series.

> -Original Message-
> From: Miquel RAYNAL [mailto:miquel.ray...@free-electrons.com]
> Sent: Friday, December 29, 2017 2:25 AM
> To: Naga Sureshkumar Relli 
> Cc: boris.brezil...@free-electrons.com; rich...@nod.at;
> computersforpe...@gmail.com; marek.va...@gmail.com;
> cyrille.pitc...@wedev4u.fr; Naga Sureshkumar Relli ;
> nagasures...@gmail.com; linux-kernel@vger.kernel.org; linux-
> m...@lists.infradead.org; Punnaiah Choudary Kalluri ;
> Michal Simek ; dw...@infradead.org
> Subject: Re: [PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash
> Controller
> 
> Hello,
> 
> Thanks for contributing this driver.
> 
> As you may know, the NAND framework is currently moving to an interface
> called ->exec_op(). Please look at the l2-mtd -or linux-next- tree to see 
> what this
> is (drivers/mtd/nand/nand_base.c is quite well documented about this
> interface).
> 
> New drivers should drop their ->cmdfunc() / ->cmd_ctrl() /
> ->read/write_byte/word/buf() implementations and instead switch to
> ->exec_op(). I know this is a significant amount of work but do not
> hesitate to ask if you need some help.

Ok I will update the driver as per new exec_op() update.
Let me go through this interface.
> 
> You may take the Marvell NAND controller driver as example of how to
> implement it (rework also currently under review):
> https://www.spinics.net/lists/arm-kernel/msg624246.html
Ok, I will take a look into that driver.

> 
> Otherwise there are some comments below. I am really not a NAND god, so
> don't take them as pure truth :)
Thanks for reviewing this driver. 
> 
> Thank you,
> Miquèl
> 
> On Thu, 14 Dec 2017 19:14:45 +0530
> Naga Sureshkumar Relli  wrote:
> 
> > Added the basic driver for Arasan NAND Flash Controller used in Zynq
> > UltraScale+ MPSoC. It supports only Hw ECC and upto 24bit correction.
> >
> > Signed-off-by: Naga Sureshkumar Relli 
> > Signed-off-by: Punnaiah Choudary Kalluri 
> > ---
> > Changes in v9:
> >  - Added the SPDX tags
> > Changes in v8:
> >  - Implemented setup_data_interface hook
> >  - fixed checkpatch --strict warnings
> >  - Added anfc_config_ecc in read_page_hwecc
> >  - Fixed returning status value by reading flash status in read_byte()
> >instead of reading previous value.
> > Changes in v7:
> > - Implemented Marek suggestions and comments
> > - Corrected the acronyms those should be in caps
> > - Modified kconfig/Make file to keep arasan entry in sorted order
> > - Added is_vmlloc_addr check
> > - Used ioread/write32_rep variants to avoid compilation error for
> > intel platforms
> > - separated PIO and DMA mode read/write functions
> > - Minor cleanup
> > Chnages in v6:
> > - Addressed most of the Brian and Boris comments
> > - Separated the nandchip from the nand controller
> > - Removed the ecc lookup table from driver
> > - Now use framework nand waitfunction and readoob
> > - Fixed the compiler warning
> > - Adapted the new frameowrk changes related to ecc and ooblayout
> > - Disabled the clocks after the nand_reelase
> > - Now using only one completion object
> > - Boris suggessions like adapting cmd_ctrl and rework on read/write
> > byte are not implemented and i will patch them later
> > - Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr
> > will implement later once the basic driver is mainlined.
> > Changes in v5:
> > - Renamed the driver filei as arasan_nand.c
> > - Fixed all comments relaqted coding style
> > - Fixed comments related to propagating the errors
> > - Modified the anfc_write_page_hwecc as per the write_page
> >   prototype
> > Changes in v4:
> > - Added support for onfi timing mode configuration
> > - Added clock suort
> > - Added support for multiple chipselects Changes in v3:
> > - Removed unused variables
> > - Avoided busy loop and used jifies based implementation
> > - Fixed compiler warnings "right shift count >= width of type"
> > - Removed unneeded codei and improved error reporting
> > - Added onfi version check to ensure reading the valid address cycles
> > Changes in v2:
> > - Added missing of.h to avoid kbuild system report erro
> > ---
> >  drivers/mtd/nand/Kconfig   |8 +
> >  drivers/mtd/nand/Makefile  |1 +
> >  drivers/mtd/nand/arasan_nand.c | 1018
> >  3 files changed, 1027
> > insertions(+) create mode 100644 drivers/mtd/nand/arasan_nand.c
> >
> > diff --git a/drivers/m

Re: [PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash Controller

[Miquel RAYNAL]

Hello,

Thanks for contributing this driver.

As you may know, the NAND framework is currently moving to an interface
called ->exec_op(). Please look at the l2-mtd -or linux-next- tree to
see what this is (drivers/mtd/nand/nand_base.c is quite well
documented about this interface).

New drivers should drop their ->cmdfunc() / ->cmd_ctrl() /
->read/write_byte/word/buf() implementations and instead switch to
->exec_op(). I know this is a significant amount of work but do not
hesitate to ask if you need some help.

You may take the Marvell NAND controller driver as example of how to
implement it (rework also currently under review):
https://www.spinics.net/lists/arm-kernel/msg624246.html

Otherwise there are some comments below. I am really not a NAND god, so
don't take them as pure truth :)

Thank you,
Miquèl

On Thu, 14 Dec 2017 19:14:45 +0530
Naga Sureshkumar Relli  wrote:

> Added the basic driver for Arasan NAND Flash Controller used in
> Zynq UltraScale+ MPSoC. It supports only Hw ECC and upto 24bit
> correction.
> 
> Signed-off-by: Naga Sureshkumar Relli 
> Signed-off-by: Punnaiah Choudary Kalluri 
> ---
> Changes in v9:
>  - Added the SPDX tags
> Changes in v8:
>  - Implemented setup_data_interface hook
>  - fixed checkpatch --strict warnings
>  - Added anfc_config_ecc in read_page_hwecc
>  - Fixed returning status value by reading flash status in read_byte()
>instead of reading previous value.
> Changes in v7:
> - Implemented Marek suggestions and comments
> - Corrected the acronyms those should be in caps
> - Modified kconfig/Make file to keep arasan entry in sorted order
> - Added is_vmlloc_addr check
> - Used ioread/write32_rep variants to avoid compilation error for
> intel platforms
> - separated PIO and DMA mode read/write functions
> - Minor cleanup
> Chnages in v6:
> - Addressed most of the Brian and Boris comments
> - Separated the nandchip from the nand controller
> - Removed the ecc lookup table from driver
> - Now use framework nand waitfunction and readoob
> - Fixed the compiler warning
> - Adapted the new frameowrk changes related to ecc and ooblayout
> - Disabled the clocks after the nand_reelase
> - Now using only one completion object
> - Boris suggessions like adapting cmd_ctrl and rework on read/write
> byte are not implemented and i will patch them later
> - Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr
> will implement later once the basic driver is mainlined.
> Changes in v5:
> - Renamed the driver filei as arasan_nand.c
> - Fixed all comments relaqted coding style
> - Fixed comments related to propagating the errors
> - Modified the anfc_write_page_hwecc as per the write_page
>   prototype
> Changes in v4:
> - Added support for onfi timing mode configuration
> - Added clock suort
> - Added support for multiple chipselects
> Changes in v3:
> - Removed unused variables
> - Avoided busy loop and used jifies based implementation
> - Fixed compiler warnings "right shift count >= width of type"
> - Removed unneeded codei and improved error reporting
> - Added onfi version check to ensure reading the valid address cycles
> Changes in v2:
> - Added missing of.h to avoid kbuild system report erro
> ---
>  drivers/mtd/nand/Kconfig   |8 +
>  drivers/mtd/nand/Makefile  |1 +
>  drivers/mtd/nand/arasan_nand.c | 1018
>  3 files changed, 1027
> insertions(+) create mode 100644 drivers/mtd/nand/arasan_nand.c
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 3f2036f31da4..bdc97510f758 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -40,6 +40,14 @@ config MTD_SM_COMMON
>   tristate
>   default n
>  
> +config MTD_NAND_ARASAN
> + tristate "Support for Arasan Nand Flash controller"
> + depends on HAS_IOMEM
> + depends on HAS_DMA
> + help
> +   Enables the driver for the Arasan NAND Flash controller on
> +   Zynq UltraScale+ MPSoC.
> +
>  config MTD_NAND_DENALI
>   tristate
>  
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 6e2db700d923..b96965a95daf 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_NAND_ECC)+=
> nand_ecc.o obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o
>  obj-$(CONFIG_MTD_SM_COMMON)  += sm_common.o
>  
> +obj-$(CONFIG_MTD_NAND_ARASAN)+= arasan_nand.o
>  obj-$(CONFIG_MTD_NAND_CAFE)  += cafe_nand.o
>  obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o
>  obj-$(CONFIG_MTD_NAND_DENALI)+= denali.o
> diff --git a/drivers/mtd/nand/arasan_nand.c
> b/drivers/mtd/nand/arasan_nand.c new file mode 100644
> index ..89c06b70b65d
> --- /dev/null
> +++ b/drivers/mtd/nand/arasan_nand.c
> @@ -0,0 +1,1018 @@
> +/*
> + * Arasan NAND Flash Controller Driver
> + *
> + * Copyright (C) 2014 

Re: [PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash Controller

[Miquel RAYNAL]

Hello,

Thanks for contributing this driver.

As you may know, the NAND framework is currently moving to an interface
called ->exec_op(). Please look at the l2-mtd -or linux-next- tree to
see what this is (drivers/mtd/nand/nand_base.c is quite well
documented about this interface).

New drivers should drop their ->cmdfunc() / ->cmd_ctrl() /
->read/write_byte/word/buf() implementations and instead switch to
->exec_op(). I know this is a significant amount of work but do not
hesitate to ask if you need some help.

You may take the Marvell NAND controller driver as example of how to
implement it (rework also currently under review):
https://www.spinics.net/lists/arm-kernel/msg624246.html

Otherwise there are some comments below. I am really not a NAND god, so
don't take them as pure truth :)

Thank you,
Miquèl

On Thu, 14 Dec 2017 19:14:45 +0530
Naga Sureshkumar Relli  wrote:

> Added the basic driver for Arasan NAND Flash Controller used in
> Zynq UltraScale+ MPSoC. It supports only Hw ECC and upto 24bit
> correction.
> 
> Signed-off-by: Naga Sureshkumar Relli 
> Signed-off-by: Punnaiah Choudary Kalluri 
> ---
> Changes in v9:
>  - Added the SPDX tags
> Changes in v8:
>  - Implemented setup_data_interface hook
>  - fixed checkpatch --strict warnings
>  - Added anfc_config_ecc in read_page_hwecc
>  - Fixed returning status value by reading flash status in read_byte()
>instead of reading previous value.
> Changes in v7:
> - Implemented Marek suggestions and comments
> - Corrected the acronyms those should be in caps
> - Modified kconfig/Make file to keep arasan entry in sorted order
> - Added is_vmlloc_addr check
> - Used ioread/write32_rep variants to avoid compilation error for
> intel platforms
> - separated PIO and DMA mode read/write functions
> - Minor cleanup
> Chnages in v6:
> - Addressed most of the Brian and Boris comments
> - Separated the nandchip from the nand controller
> - Removed the ecc lookup table from driver
> - Now use framework nand waitfunction and readoob
> - Fixed the compiler warning
> - Adapted the new frameowrk changes related to ecc and ooblayout
> - Disabled the clocks after the nand_reelase
> - Now using only one completion object
> - Boris suggessions like adapting cmd_ctrl and rework on read/write
> byte are not implemented and i will patch them later
> - Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr
> will implement later once the basic driver is mainlined.
> Changes in v5:
> - Renamed the driver filei as arasan_nand.c
> - Fixed all comments relaqted coding style
> - Fixed comments related to propagating the errors
> - Modified the anfc_write_page_hwecc as per the write_page
>   prototype
> Changes in v4:
> - Added support for onfi timing mode configuration
> - Added clock suort
> - Added support for multiple chipselects
> Changes in v3:
> - Removed unused variables
> - Avoided busy loop and used jifies based implementation
> - Fixed compiler warnings "right shift count >= width of type"
> - Removed unneeded codei and improved error reporting
> - Added onfi version check to ensure reading the valid address cycles
> Changes in v2:
> - Added missing of.h to avoid kbuild system report erro
> ---
>  drivers/mtd/nand/Kconfig   |8 +
>  drivers/mtd/nand/Makefile  |1 +
>  drivers/mtd/nand/arasan_nand.c | 1018
>  3 files changed, 1027
> insertions(+) create mode 100644 drivers/mtd/nand/arasan_nand.c
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 3f2036f31da4..bdc97510f758 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -40,6 +40,14 @@ config MTD_SM_COMMON
>   tristate
>   default n
>  
> +config MTD_NAND_ARASAN
> + tristate "Support for Arasan Nand Flash controller"
> + depends on HAS_IOMEM
> + depends on HAS_DMA
> + help
> +   Enables the driver for the Arasan NAND Flash controller on
> +   Zynq UltraScale+ MPSoC.
> +
>  config MTD_NAND_DENALI
>   tristate
>  
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 6e2db700d923..b96965a95daf 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_NAND_ECC)+=
> nand_ecc.o obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o
>  obj-$(CONFIG_MTD_SM_COMMON)  += sm_common.o
>  
> +obj-$(CONFIG_MTD_NAND_ARASAN)+= arasan_nand.o
>  obj-$(CONFIG_MTD_NAND_CAFE)  += cafe_nand.o
>  obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o
>  obj-$(CONFIG_MTD_NAND_DENALI)+= denali.o
> diff --git a/drivers/mtd/nand/arasan_nand.c
> b/drivers/mtd/nand/arasan_nand.c new file mode 100644
> index ..89c06b70b65d
> --- /dev/null
> +++ b/drivers/mtd/nand/arasan_nand.c
> @@ -0,0 +1,1018 @@
> +/*
> + * Arasan NAND Flash Controller Driver
> + *
> + * Copyright (C) 2014 - 2017 Xilinx, Inc.
> + * Author: Punnaiah Choudary Kalluri 
> + *
> + * 

[PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash Controller

[Naga Sureshkumar Relli]

Added the basic driver for Arasan NAND Flash Controller used in
Zynq UltraScale+ MPSoC. It supports only Hw ECC and upto 24bit
correction.

Signed-off-by: Naga Sureshkumar Relli 
Signed-off-by: Punnaiah Choudary Kalluri 
---
Changes in v9:
 - Added the SPDX tags
Changes in v8:
 - Implemented setup_data_interface hook
 - fixed checkpatch --strict warnings
 - Added anfc_config_ecc in read_page_hwecc
 - Fixed returning status value by reading flash status in read_byte()
   instead of reading previous value.
Changes in v7:
- Implemented Marek suggestions and comments
- Corrected the acronyms those should be in caps
- Modified kconfig/Make file to keep arasan entry in sorted order
- Added is_vmlloc_addr check
- Used ioread/write32_rep variants to avoid compilation error for intel
  platforms
- separated PIO and DMA mode read/write functions
- Minor cleanup
Chnages in v6:
- Addressed most of the Brian and Boris comments
- Separated the nandchip from the nand controller
- Removed the ecc lookup table from driver
- Now use framework nand waitfunction and readoob
- Fixed the compiler warning
- Adapted the new frameowrk changes related to ecc and ooblayout
- Disabled the clocks after the nand_reelase
- Now using only one completion object
- Boris suggessions like adapting cmd_ctrl and rework on read/write byte
  are not implemented and i will patch them later
- Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr will
  implement later once the basic driver is mainlined.
Changes in v5:
- Renamed the driver filei as arasan_nand.c
- Fixed all comments relaqted coding style
- Fixed comments related to propagating the errors
- Modified the anfc_write_page_hwecc as per the write_page
  prototype
Changes in v4:
- Added support for onfi timing mode configuration
- Added clock suort
- Added support for multiple chipselects
Changes in v3:
- Removed unused variables
- Avoided busy loop and used jifies based implementation
- Fixed compiler warnings "right shift count >= width of type"
- Removed unneeded codei and improved error reporting
- Added onfi version check to ensure reading the valid address cycles
Changes in v2:
- Added missing of.h to avoid kbuild system report erro
---
 drivers/mtd/nand/Kconfig   |8 +
 drivers/mtd/nand/Makefile  |1 +
 drivers/mtd/nand/arasan_nand.c | 1018 
 3 files changed, 1027 insertions(+)
 create mode 100644 drivers/mtd/nand/arasan_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3f2036f31da4..bdc97510f758 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -40,6 +40,14 @@ config MTD_SM_COMMON
tristate
default n
 
+config MTD_NAND_ARASAN
+   tristate "Support for Arasan Nand Flash controller"
+   depends on HAS_IOMEM
+   depends on HAS_DMA
+   help
+ Enables the driver for the Arasan NAND Flash controller on
+ Zynq UltraScale+ MPSoC.
+
 config MTD_NAND_DENALI
tristate
 
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6e2db700d923..b96965a95daf 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_NAND_ECC)  += nand_ecc.o
 obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o
 obj-$(CONFIG_MTD_SM_COMMON)+= sm_common.o
 
+obj-$(CONFIG_MTD_NAND_ARASAN)  += arasan_nand.o
 obj-$(CONFIG_MTD_NAND_CAFE)+= cafe_nand.o
 obj-$(CONFIG_MTD_NAND_AMS_DELTA)   += ams-delta.o
 obj-$(CONFIG_MTD_NAND_DENALI)  += denali.o
diff --git a/drivers/mtd/nand/arasan_nand.c b/drivers/mtd/nand/arasan_nand.c
new file mode 100644
index ..89c06b70b65d
--- /dev/null
+++ b/drivers/mtd/nand/arasan_nand.c
@@ -0,0 +1,1018 @@
+/*
+ * Arasan NAND Flash Controller Driver
+ *
+ * Copyright (C) 2014 - 2017 Xilinx, Inc.
+ * Author: Punnaiah Choudary Kalluri 
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRIVER_NAME"arasan_nand"
+#define EVNT_TIMEOUT_MSEC  1000
+
+#define PKT_OFST   0x00
+#define MEM_ADDR1_OFST 0x04
+#define MEM_ADDR2_OFST 0x08
+#define CMD_OFST   0x0C
+#define PROG_OFST  0x10
+#define INTR_STS_EN_OFST   0x14
+#define INTR_SIG_EN_OFST   0x18
+#define INTR_STS_OFST  0x1C
+#define READY_STS_OFST 0x20
+#define DMA_ADDR1_OFST 0x24
+#define FLASH_STS_OFST 0x28
+#define DATA_PORT_OFST 0x30
+#define ECC_OFST   0x34
+#define ECC_ERR_CNT_OFST   0x38
+#define ECC_SPR_CMD_OFST   0x3C
+#define ECC_ERR_CNT_1BIT_OFST  0x40
+#define ECC_ERR_CNT_2BIT_OFST   

[PATCH v9 2/2] mtd: nand: Add support for Arasan NAND Flash Controller

[Naga Sureshkumar Relli]

Added the basic driver for Arasan NAND Flash Controller used in
Zynq UltraScale+ MPSoC. It supports only Hw ECC and upto 24bit
correction.

Signed-off-by: Naga Sureshkumar Relli 
Signed-off-by: Punnaiah Choudary Kalluri 
---
Changes in v9:
 - Added the SPDX tags
Changes in v8:
 - Implemented setup_data_interface hook
 - fixed checkpatch --strict warnings
 - Added anfc_config_ecc in read_page_hwecc
 - Fixed returning status value by reading flash status in read_byte()
   instead of reading previous value.
Changes in v7:
- Implemented Marek suggestions and comments
- Corrected the acronyms those should be in caps
- Modified kconfig/Make file to keep arasan entry in sorted order
- Added is_vmlloc_addr check
- Used ioread/write32_rep variants to avoid compilation error for intel
  platforms
- separated PIO and DMA mode read/write functions
- Minor cleanup
Chnages in v6:
- Addressed most of the Brian and Boris comments
- Separated the nandchip from the nand controller
- Removed the ecc lookup table from driver
- Now use framework nand waitfunction and readoob
- Fixed the compiler warning
- Adapted the new frameowrk changes related to ecc and ooblayout
- Disabled the clocks after the nand_reelase
- Now using only one completion object
- Boris suggessions like adapting cmd_ctrl and rework on read/write byte
  are not implemented and i will patch them later
- Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr will
  implement later once the basic driver is mainlined.
Changes in v5:
- Renamed the driver filei as arasan_nand.c
- Fixed all comments relaqted coding style
- Fixed comments related to propagating the errors
- Modified the anfc_write_page_hwecc as per the write_page
  prototype
Changes in v4:
- Added support for onfi timing mode configuration
- Added clock suort
- Added support for multiple chipselects
Changes in v3:
- Removed unused variables
- Avoided busy loop and used jifies based implementation
- Fixed compiler warnings "right shift count >= width of type"
- Removed unneeded codei and improved error reporting
- Added onfi version check to ensure reading the valid address cycles
Changes in v2:
- Added missing of.h to avoid kbuild system report erro
---
 drivers/mtd/nand/Kconfig   |8 +
 drivers/mtd/nand/Makefile  |1 +
 drivers/mtd/nand/arasan_nand.c | 1018 
 3 files changed, 1027 insertions(+)
 create mode 100644 drivers/mtd/nand/arasan_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3f2036f31da4..bdc97510f758 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -40,6 +40,14 @@ config MTD_SM_COMMON
tristate
default n
 
+config MTD_NAND_ARASAN
+   tristate "Support for Arasan Nand Flash controller"
+   depends on HAS_IOMEM
+   depends on HAS_DMA
+   help
+ Enables the driver for the Arasan NAND Flash controller on
+ Zynq UltraScale+ MPSoC.
+
 config MTD_NAND_DENALI
tristate
 
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6e2db700d923..b96965a95daf 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_NAND_ECC)  += nand_ecc.o
 obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o
 obj-$(CONFIG_MTD_SM_COMMON)+= sm_common.o
 
+obj-$(CONFIG_MTD_NAND_ARASAN)  += arasan_nand.o
 obj-$(CONFIG_MTD_NAND_CAFE)+= cafe_nand.o
 obj-$(CONFIG_MTD_NAND_AMS_DELTA)   += ams-delta.o
 obj-$(CONFIG_MTD_NAND_DENALI)  += denali.o
diff --git a/drivers/mtd/nand/arasan_nand.c b/drivers/mtd/nand/arasan_nand.c
new file mode 100644
index ..89c06b70b65d
--- /dev/null
+++ b/drivers/mtd/nand/arasan_nand.c
@@ -0,0 +1,1018 @@
+/*
+ * Arasan NAND Flash Controller Driver
+ *
+ * Copyright (C) 2014 - 2017 Xilinx, Inc.
+ * Author: Punnaiah Choudary Kalluri 
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRIVER_NAME"arasan_nand"
+#define EVNT_TIMEOUT_MSEC  1000
+
+#define PKT_OFST   0x00
+#define MEM_ADDR1_OFST 0x04
+#define MEM_ADDR2_OFST 0x08
+#define CMD_OFST   0x0C
+#define PROG_OFST  0x10
+#define INTR_STS_EN_OFST   0x14
+#define INTR_SIG_EN_OFST   0x18
+#define INTR_STS_OFST  0x1C
+#define READY_STS_OFST 0x20
+#define DMA_ADDR1_OFST 0x24
+#define FLASH_STS_OFST 0x28
+#define DATA_PORT_OFST 0x30
+#define ECC_OFST   0x34
+#define ECC_ERR_CNT_OFST   0x38
+#define ECC_SPR_CMD_OFST   0x3C
+#define ECC_ERR_CNT_1BIT_OFST  0x40
+#define ECC_ERR_CNT_2BIT_OFST  0x44
+#define DMA_ADDR0_OFST 0x50