Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Arnd, Hello Olof, Hello Kevin,
I checked the git log of Linux 4.1-rc7 from Linus, he says Linux 4.1
will have an rc8, so we may have time to review the following two pull
requests from Wei Xu?
[GIT PULL v2]Hisilicon 64-bit SoC changes for 4.2
[GIT PULL]Hisilicon 64-bit soc hi6220 DT changes for 4.2
Thanks for your time.
BR,
Bintian
On 2015/6/9 9:39, Bintian wrote:
Hello Shawn,
On 2015/6/9 8:55, Shawn Guo wrote:
A minor random comment below.
On Sat, May 30, 2015 at 09:51:00AM +0800, Bintian Wang wrote:
+ao_ctrl: ao_ctrl {
+compatible = "hisilicon,hi6220-aoctrl", "syscon";
+reg = <0x0 0xf780 0x0 0x2000>;
+#clock-cells = <1>;
+};
+
+sys_ctrl: sys_ctrl {
+compatible = "hisilicon,hi6220-sysctrl", "syscon";
+reg = <0x0 0xf703 0x0 0x2000>;
+#clock-cells = <1>;
+};
+
+media_ctrl: media_ctrl {
+compatible = "hisilicon,hi6220-mediactrl", "syscon";
+reg = <0x0 0xf441 0x0 0x1000>;
+#clock-cells = <1>;
+};
+
+pm_ctrl: pm_ctrl {
An unit-address should be coded in the node name, when it has a 'reg'
property.
Thanks for your suggestion, Rob also gives me the same suggestion :)
In fact, I added the reg to node name in the "[GIT PULL]Hisilicon 64-bit
soc hi6220 DT changes for 4.2", but it seems the pull is too late for
kernel 4.2, I will prepare it for 4.3.
Thanks,
Bintian
Shawn
+compatible = "hisilicon,hi6220-pmctrl", "syscon";
+reg = <0x0 0xf7032000 0x0 0x1000>;
+#clock-cells = <1>;
+};
.
.
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Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Shawn,
On 2015/6/9 8:55, Shawn Guo wrote:
A minor random comment below.
On Sat, May 30, 2015 at 09:51:00AM +0800, Bintian Wang wrote:
+ ao_ctrl: ao_ctrl {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0x0 0xf780 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ sys_ctrl: sys_ctrl {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ media_ctrl: media_ctrl {
+ compatible = "hisilicon,hi6220-mediactrl", "syscon";
+ reg = <0x0 0xf441 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pm_ctrl: pm_ctrl {
An unit-address should be coded in the node name, when it has a 'reg'
property.
Thanks for your suggestion, Rob also gives me the same suggestion :)
In fact, I added the reg to node name in the "[GIT PULL]Hisilicon 64-bit
soc hi6220 DT changes for 4.2", but it seems the pull is too late for
kernel 4.2, I will prepare it for 4.3.
Thanks,
Bintian
Shawn
+ compatible = "hisilicon,hi6220-pmctrl", "syscon";
+ reg = <0x0 0xf7032000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
.
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
A minor random comment below.
On Sat, May 30, 2015 at 09:51:00AM +0800, Bintian Wang wrote:
> + ao_ctrl: ao_ctrl {
> + compatible = "hisilicon,hi6220-aoctrl", "syscon";
> + reg = <0x0 0xf780 0x0 0x2000>;
> + #clock-cells = <1>;
> + };
> +
> + sys_ctrl: sys_ctrl {
> + compatible = "hisilicon,hi6220-sysctrl", "syscon";
> + reg = <0x0 0xf703 0x0 0x2000>;
> + #clock-cells = <1>;
> + };
> +
> + media_ctrl: media_ctrl {
> + compatible = "hisilicon,hi6220-mediactrl", "syscon";
> + reg = <0x0 0xf441 0x0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pm_ctrl: pm_ctrl {
An unit-address should be coded in the node name, when it has a 'reg'
property.
Shawn
> + compatible = "hisilicon,hi6220-pmctrl", "syscon";
> + reg = <0x0 0xf7032000 0x0 0x1000>;
> + #clock-cells = <1>;
> + };
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Mark, Rob and other ARM64 DT maintainers,
Could you help to ack this patch?
Thanks for your time.
Bintian
On 2015/5/30 9:51, Bintian Wang wrote:
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Also add dts file to support HiKey development board which
based on Hi6220 SoC.
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Yiping Xu
Tested-by: Will Deacon
Tested-by: Tyler Baker
Tested-by: Kevin Hilman
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/hisilicon/Makefile |5 +
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172
4 files changed, 209 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index ad26a75..38913be 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
+dts-dirs += hisilicon
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
new file mode 100644
index 000..fa81a6e
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
new file mode 100644
index 000..e36a539
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -0,0 +1,31 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e0 0x0010;
+
+#include "hi6220.dtsi"
+
+/ {
+ model = "HiKey Development Board";
+ compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x4000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
new file mode 100644
index 000..229937f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -0,0 +1,172 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "hisilicon,hi6220";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+
[PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Also add dts file to support HiKey development board which
based on Hi6220 SoC.
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Yiping Xu
Tested-by: Will Deacon
Tested-by: Tyler Baker
Tested-by: Kevin Hilman
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/hisilicon/Makefile |5 +
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172
4 files changed, 209 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index ad26a75..38913be 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
+dts-dirs += hisilicon
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
new file mode 100644
index 000..fa81a6e
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
new file mode 100644
index 000..e36a539
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -0,0 +1,31 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e0 0x0010;
+
+#include "hi6220.dtsi"
+
+/ {
+ model = "HiKey Development Board";
+ compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x4000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
new file mode 100644
index 000..229937f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -0,0 +1,172 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "hisilicon,hi6220";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enabl
