[Patch V6 10/10] ARM: dts: Model IPQ LPASS audio hardware
From: Kenneth Westfield
Model the Qualcomm Technologies LPASS hardware for
the ipq806x SOC.
Signed-off-by: Kenneth Westfield
Acked-by: Banajit Goswami
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index
cb225dafe97cd83c9ae4cc19482ed55d4a71b8b3..dd5cbb33cc2d89be57494e05b7477352358affa5
100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,7 @@
#include "skeleton.dtsi"
#include
+#include
#include
/ {
@@ -96,6 +97,24 @@
cpu-offset = <0x8>;
};
+ lpass@2810 {
+ compatible = "qcom,lpass-cpu";
+ status = "disabled";
+ clocks = < AHBIX_CLK>,
+ < MI2S_OSR_CLK>,
+ < MI2S_BIT_CLK>;
+ clock-names = "ahbix-clk",
+ "mi2s-osr-clk",
+ "mi2s-bit-clk";
+ interrupts = <0 85 1>;
+ interrupt-names = "lpass-irq-lpaif";
+ reg = <0x2810 0x1>;
+ reg-names = "lpass-lpaif";
+ qcom,adsp {
+ status = "disabled";
+ };
+ };
+
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@@ -273,6 +292,13 @@
qcom,controller-type = "pmic-arbiter";
};
+ lcc: clock-controller@2800 {
+ compatible = "qcom,lcc-ipq8064";
+ reg = <0x2800 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
gcc: clock-controller@90 {
compatible = "qcom,gcc-ipq8064";
reg = <0x0090 0x4000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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[Patch V6 10/10] ARM: dts: Model IPQ LPASS audio hardware
From: Kenneth Westfield kwest...@codeaurora.org
Model the Qualcomm Technologies LPASS hardware for
the ipq806x SOC.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index
cb225dafe97cd83c9ae4cc19482ed55d4a71b8b3..dd5cbb33cc2d89be57494e05b7477352358affa5
100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,6 +2,7 @@
#include skeleton.dtsi
#include dt-bindings/clock/qcom,gcc-ipq806x.h
+#include dt-bindings/clock/qcom,lcc-ipq806x.h
#include dt-bindings/soc/qcom,gsbi.h
/ {
@@ -96,6 +97,24 @@
cpu-offset = 0x8;
};
+ lpass@2810 {
+ compatible = qcom,lpass-cpu;
+ status = disabled;
+ clocks = lcc AHBIX_CLK,
+ lcc MI2S_OSR_CLK,
+ lcc MI2S_BIT_CLK;
+ clock-names = ahbix-clk,
+ mi2s-osr-clk,
+ mi2s-bit-clk;
+ interrupts = 0 85 1;
+ interrupt-names = lpass-irq-lpaif;
+ reg = 0x2810 0x1;
+ reg-names = lpass-lpaif;
+ qcom,adsp {
+ status = disabled;
+ };
+ };
+
acc0: clock-controller@2088000 {
compatible = qcom,kpss-acc-v1;
reg = 0x02088000 0x1000, 0x02008000 0x1000;
@@ -273,6 +292,13 @@
qcom,controller-type = pmic-arbiter;
};
+ lcc: clock-controller@2800 {
+ compatible = qcom,lcc-ipq8064;
+ reg = 0x2800 0x1000;
+ #clock-cells = 1;
+ #reset-cells = 1;
+ };
+
gcc: clock-controller@90 {
compatible = qcom,gcc-ipq8064;
reg = 0x0090 0x4000;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
