[RESEND PATCH 6/6] ARM: dts: mt6580: enable basic SMP bringup for mt6580
Add arch timer node to enable arch-timer support. MT6580 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This set cpu enable-method to enable SMP.
---
arch/arm/boot/dts/mt6580.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index a974830..a7071b38 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -23,26 +23,31 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "mediatek,mt6580-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
+ clock-frequency = <17>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
+ clock-frequency = <17>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
+ clock-frequency = <17>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
+ clock-frequency = <17>;
};
};
@@ -72,6 +77,21 @@
};
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
--
1.8.1.1.dirty
--
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[RESEND PATCH 6/6] ARM: dts: mt6580: enable basic SMP bringup for mt6580
Add arch timer node to enable arch-timer support. MT6580 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.
This set cpu enable-method to enable SMP.
---
arch/arm/boot/dts/mt6580.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index a974830..a7071b38 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -23,26 +23,31 @@
cpus {
#address-cells = 1;
#size-cells = 0;
+ enable-method = mediatek,mt6580-smp;
cpu@0 {
device_type = cpu;
compatible = arm,cortex-a7;
reg = 0x0;
+ clock-frequency = 17;
};
cpu@1 {
device_type = cpu;
compatible = arm,cortex-a7;
reg = 0x1;
+ clock-frequency = 17;
};
cpu@2 {
device_type = cpu;
compatible = arm,cortex-a7;
reg = 0x2;
+ clock-frequency = 17;
};
cpu@3 {
device_type = cpu;
compatible = arm,cortex-a7;
reg = 0x3;
+ clock-frequency = 17;
};
};
@@ -72,6 +77,21 @@
};
};
+ timer {
+ compatible = arm,armv7-timer;
+ interrupt-parent = gic;
+ interrupts = GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW),
+GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW),
+GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW),
+GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW);
+ clock-frequency = 1300;
+ arm,cpu-registers-not-fw-configured;
+ };
+
soc {
#address-cells = 1;
#size-cells = 1;
--
1.8.1.1.dirty
--
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