Re: [RESEND v1 net-next 4/5] stmmac: intel: add support for multi-vector msi and msi-x

[Jakub Kicinski]

On Tue, 16 Mar 2021 20:18:22 +0800 Voon Weifeng wrote:
> From: Ong Boon Leong 
> 
> Intel mgbe controller supports multi-vector interrupts:
> msi_rx_vec0,2,4,6,8,10,12,14
> msi_tx_vec1,3,5,7,9,11,13,15
> msi_sfty_ue_vec   26
> msi_sfty_ce_vec   27
> msi_lpi_vec   28
> msi_mac_vec   29
> 
> During probe(), the driver will starts with request allocation for
> multi-vector interrupts. If it fails, then it will automatically fallback
> to request allocation for single interrupts.
> 
> Signed-off-by: Ong Boon Leong 
> Co-developed-by: Voon Weifeng 
> Signed-off-by: Voon Weifeng 

> +
> +static int stmmac_config_multi_msi(struct pci_dev *pdev,
> +struct plat_stmmacenet_data *plat,
> +struct stmmac_resources *res)
> +{
> + int ret;
> + int i;
> +
> + ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
> + PCI_IRQ_MSI | PCI_IRQ_MSIX);
> + if (ret < 0) {
> + dev_info(>dev, "%s: multi MSI enablement failed\n",
> +  __func__);
> + return ret;
> + }
> +
> + if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
> + plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
> + dev_info(>dev, "%s: Invalid RX & TX vector defined\n",
> +  __func__);
> + return -1;

free_irq_vectors?  Or move the check before alloc if possible.

> + }


> @@ -699,6 +786,19 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
>   writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
>   }
>  
> + ret = stmmac_config_multi_msi(pdev, plat, );
> + if (!ret)
> + goto msi_done;

Please don't use gotos where an if statement would do perfectly well.

> + ret = stmmac_config_single_msi(pdev, plat, );
> + if (ret) {
> + dev_err(>dev, "%s: ERROR: failed to enable IRQ\n",
> + __func__);
> + return ret;

return? isn't there some cleanup that needs to happen before exiting?

> + }
> +
> +msi_done:
> +
>   ret = stmmac_dvr_probe(>dev, plat, );
>   if (ret) {
>   pci_free_irq_vectors(pdev);

[RESEND v1 net-next 4/5] stmmac: intel: add support for multi-vector msi and msi-x

[Voon Weifeng]

From: Ong Boon Leong 

Intel mgbe controller supports multi-vector interrupts:
msi_rx_vec  0,2,4,6,8,10,12,14
msi_tx_vec  1,3,5,7,9,11,13,15
msi_sfty_ue_vec 26
msi_sfty_ce_vec 27
msi_lpi_vec 28
msi_mac_vec 29

During probe(), the driver will starts with request allocation for
multi-vector interrupts. If it fails, then it will automatically fallback
to request allocation for single interrupts.

Signed-off-by: Ong Boon Leong 
Co-developed-by: Voon Weifeng 
Signed-off-by: Voon Weifeng 
---
 .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 112 +-
 1 file changed, 106 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index c49646773871..3b01557e561b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -346,6 +346,14 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
 
+   /* Setup MSI vector offset specific to Intel mGbE controller */
+   plat->msi_mac_vec = 29;
+   plat->msi_lpi_vec = 28;
+   plat->msi_sfty_ce_vec = 27;
+   plat->msi_sfty_ue_vec = 26;
+   plat->msi_rx_base_vec = 0;
+   plat->msi_tx_base_vec = 1;
+
return 0;
 }
 
@@ -622,6 +630,79 @@ static const struct stmmac_pci_info quark_info = {
.setup = quark_default_data,
 };
 
+static int stmmac_config_single_msi(struct pci_dev *pdev,
+   struct plat_stmmacenet_data *plat,
+   struct stmmac_resources *res)
+{
+   int ret;
+
+   ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
+   if (ret < 0) {
+   dev_info(>dev, "%s: Single IRQ enablement failed\n",
+__func__);
+   return ret;
+   }
+
+   res->irq = pci_irq_vector(pdev, 0);
+   res->wol_irq = res->irq;
+   plat->multi_msi_en = 0;
+   dev_info(>dev, "%s: Single IRQ enablement successful\n",
+__func__);
+
+   return 0;
+}
+
+static int stmmac_config_multi_msi(struct pci_dev *pdev,
+  struct plat_stmmacenet_data *plat,
+  struct stmmac_resources *res)
+{
+   int ret;
+   int i;
+
+   ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
+   PCI_IRQ_MSI | PCI_IRQ_MSIX);
+   if (ret < 0) {
+   dev_info(>dev, "%s: multi MSI enablement failed\n",
+__func__);
+   return ret;
+   }
+
+   if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
+   plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
+   dev_info(>dev, "%s: Invalid RX & TX vector defined\n",
+__func__);
+   return -1;
+   }
+
+   /* For RX MSI */
+   for (i = 0; i < plat->rx_queues_to_use; i++) {
+   res->rx_irq[i] = pci_irq_vector(pdev,
+   plat->msi_rx_base_vec + i * 2);
+   }
+
+   /* For TX MSI */
+   for (i = 0; i < plat->tx_queues_to_use; i++) {
+   res->tx_irq[i] = pci_irq_vector(pdev,
+   plat->msi_tx_base_vec + i * 2);
+   }
+
+   if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
+   res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
+   if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
+   res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
+   if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
+   res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
+   if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
+   res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
+   if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
+   res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
+
+   plat->multi_msi_en = 1;
+   dev_info(>dev, "%s: multi MSI enablement successful\n", __func__);
+
+   return 0;
+}
+
 /**
  * intel_eth_pci_probe
  *
@@ -679,18 +760,24 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
plat->bsp_priv = intel_priv;
intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
 
+   /* Initialize all MSI vectors to invalid so that it can be set
+* according to platform data settings below.
+* Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
+*/
+   plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
+   plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
+   plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
+   plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
+   plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
+   plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
+   plat->msi_tx_base_vec =