Re: [RFC 06/11] coresight: ete: Detect ETE as one of the supported ETMs
Hi Tingwei,
On 11/14/20 5:36 AM, Tingwei Zhang wrote:
Hi Anshuman,
On Tue, Nov 10, 2020 at 08:45:04PM +0800, Anshuman Khandual wrote:
From: Suzuki K Poulose
Add ETE as one of the supported device types we support
with ETM4x driver. The devices are named following the
existing convention as ete.
ETE mandates that the trace resource status register is programmed
before the tracing is turned on. For the moment simply write to
it indicating TraceActive.
Signed-off-by: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
---
@@ -1742,6 +1758,19 @@ static int etm4_probe(struct device *dev, void
__iomem *base)
if (!desc.access.io_mem ||
fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
drvdata->skip_power_up = true;
+ major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
+ minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
+ if (drvdata->arch >= ETM_ARCH_ETE) {
+ type_name = "ete";
+ major -= 4;
+ } else {
+ type_name = "etm";
+ }
+
When trace unit supports ETE, could it be still compatible with ETMv4.4?
Can use selectively use it as ETM instead of ETE?
No. Even though most of the register sets are compatible, there are additional
restrictions and some new rules for the ETE. So, when you treat the ETE as an
ETMv4.4, you could be treading into "UNPREDICTABLE" behaviors.
Suzuki
Re: [RFC 06/11] coresight: ete: Detect ETE as one of the supported ETMs
Hi Anshuman,
On Tue, Nov 10, 2020 at 08:45:04PM +0800, Anshuman Khandual wrote:
> From: Suzuki K Poulose
>
> Add ETE as one of the supported device types we support
> with ETM4x driver. The devices are named following the
> existing convention as ete.
>
> ETE mandates that the trace resource status register is programmed
> before the tracing is turned on. For the moment simply write to
> it indicating TraceActive.
>
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> .../devicetree/bindings/arm/coresight.txt | 3 ++
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 55
> +-
> drivers/hwtracing/coresight/coresight-etm4x.h | 7 +++
> 3 files changed, 52 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
> b/Documentation/devicetree/bindings/arm/coresight.txt
> index bff96a5..784cc1b 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -40,6 +40,9 @@ its hardware characteristcs.
> - Embedded Trace Macrocell with system register access only.
> "arm,coresight-etm-sysreg";
>
> + - Embedded Trace Extensions.
> + "arm,ete"
> +
> - Coresight programmable Replicator :
> "arm,coresight-dynamic-replicator", "arm,primecell";
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 15b6e94..0fea349 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -331,6 +331,13 @@ static int etm4_enable_hw(struct etmv4_drvdata
> *drvdata)
> etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
> }
>
> + /*
> + * ETE mandates that the TRCRSR is written to before
> + * enabling it.
> + */
> + if (drvdata->arch >= ETM_ARCH_ETE)
> + etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
> +
> /* Enable the trace unit */
> etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
>
> @@ -763,13 +770,24 @@ static bool etm_init_sysreg_access(struct
> etmv4_drvdata *drvdata,
>* ETMs implementing sysreg access must implement TRCDEVARCH.
>*/
> devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
> - if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
> + switch (devarch & ETM_DEVARCH_ID_MASK) {
> + case ETM_DEVARCH_ETMv4x_ARCH:
> + *csa = (struct csdev_access) {
> + .io_mem = false,
> + .read = etm4x_sysreg_read,
> + .write = etm4x_sysreg_write,
> + };
> + break;
> + case ETM_DEVARCH_ETE_ARCH:
> + *csa = (struct csdev_access) {
> + .io_mem = false,
> + .read = ete_sysreg_read,
> + .write = ete_sysreg_write,
> + };
> + break;
> + default:
> return false;
> - *csa = (struct csdev_access) {
> - .io_mem = false,
> - .read = etm4x_sysreg_read,
> - .write = etm4x_sysreg_write,
> - };
> + }
>
> drvdata->arch = etm_devarch_to_arch(devarch);
> return true;
> @@ -1698,6 +1716,8 @@ static int etm4_probe(struct device *dev, void __iomem
> *base)
> struct etmv4_drvdata *drvdata;
> struct coresight_desc desc = { 0 };
> struct etm_init_arg init_arg = { 0 };
> + u8 major, minor;
> + char *type_name;
>
> drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> if (!drvdata)
> @@ -1724,10 +1744,6 @@ static int etm4_probe(struct device *dev, void
> __iomem *base)
> if (drvdata->cpu < 0)
> return drvdata->cpu;
>
> - desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
> - if (!desc.name)
> - return -ENOMEM;
> -
> init_arg.drvdata = drvdata;
> init_arg.csa =
>
> @@ -1742,6 +1758,19 @@ static int etm4_probe(struct device *dev, void
> __iomem *base)
> if (!desc.access.io_mem ||
> fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
> drvdata->skip_power_up = true;
> + major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
> + minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
> + if (drvdata->arch >= ETM_ARCH_ETE) {
> + type_name = "ete";
> + major -= 4;
> + } else {
> + type_name = "etm";
> + }
> +
When trace unit supports ETE, could it be still compatible with ETMv4.4?
Can use selectively use it as ETM instead of ETE?
Thanks,
Tingwei
> + desc.name = devm_kasprintf(dev, GFP_KERNEL,
> +"%s%d", type_name, drvdata->cpu);
> + if (!desc.name)
> + return -ENOMEM;
>
>
[RFC 06/11] coresight: ete: Detect ETE as one of the supported ETMs
From: Suzuki K Poulose
Add ETE as one of the supported device types we support
with ETM4x driver. The devices are named following the
existing convention as ete.
ETE mandates that the trace resource status register is programmed
before the tracing is turned on. For the moment simply write to
it indicating TraceActive.
Signed-off-by: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
---
.../devicetree/bindings/arm/coresight.txt | 3 ++
drivers/hwtracing/coresight/coresight-etm4x-core.c | 55 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 7 +++
3 files changed, 52 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt
b/Documentation/devicetree/bindings/arm/coresight.txt
index bff96a5..784cc1b 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -40,6 +40,9 @@ its hardware characteristcs.
- Embedded Trace Macrocell with system register access only.
"arm,coresight-etm-sysreg";
+ - Embedded Trace Extensions.
+ "arm,ete"
+
- Coresight programmable Replicator :
"arm,coresight-dynamic-replicator", "arm,primecell";
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 15b6e94..0fea349 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -331,6 +331,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
}
+ /*
+* ETE mandates that the TRCRSR is written to before
+* enabling it.
+*/
+ if (drvdata->arch >= ETM_ARCH_ETE)
+ etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
+
/* Enable the trace unit */
etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
@@ -763,13 +770,24 @@ static bool etm_init_sysreg_access(struct etmv4_drvdata
*drvdata,
* ETMs implementing sysreg access must implement TRCDEVARCH.
*/
devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
- if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
+ switch (devarch & ETM_DEVARCH_ID_MASK) {
+ case ETM_DEVARCH_ETMv4x_ARCH:
+ *csa = (struct csdev_access) {
+ .io_mem = false,
+ .read = etm4x_sysreg_read,
+ .write = etm4x_sysreg_write,
+ };
+ break;
+ case ETM_DEVARCH_ETE_ARCH:
+ *csa = (struct csdev_access) {
+ .io_mem = false,
+ .read = ete_sysreg_read,
+ .write = ete_sysreg_write,
+ };
+ break;
+ default:
return false;
- *csa = (struct csdev_access) {
- .io_mem = false,
- .read = etm4x_sysreg_read,
- .write = etm4x_sysreg_write,
- };
+ }
drvdata->arch = etm_devarch_to_arch(devarch);
return true;
@@ -1698,6 +1716,8 @@ static int etm4_probe(struct device *dev, void __iomem
*base)
struct etmv4_drvdata *drvdata;
struct coresight_desc desc = { 0 };
struct etm_init_arg init_arg = { 0 };
+ u8 major, minor;
+ char *type_name;
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
@@ -1724,10 +1744,6 @@ static int etm4_probe(struct device *dev, void __iomem
*base)
if (drvdata->cpu < 0)
return drvdata->cpu;
- desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
- if (!desc.name)
- return -ENOMEM;
-
init_arg.drvdata = drvdata;
init_arg.csa =
@@ -1742,6 +1758,19 @@ static int etm4_probe(struct device *dev, void __iomem
*base)
if (!desc.access.io_mem ||
fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
drvdata->skip_power_up = true;
+ major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
+ minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
+ if (drvdata->arch >= ETM_ARCH_ETE) {
+ type_name = "ete";
+ major -= 4;
+ } else {
+ type_name = "etm";
+ }
+
+ desc.name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s%d", type_name, drvdata->cpu);
+ if (!desc.name)
+ return -ENOMEM;
etm4_init_trace_id(drvdata);
etm4_set_default(>config);
@@ -1770,9 +1799,8 @@ static int etm4_probe(struct device *dev, void __iomem
*base)
etmdrvdata[drvdata->cpu] = drvdata;
- dev_info(>csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
-drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch),
-
