Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy

[Vivek Gautam]

On Wed, Dec 28, 2016 at 3:05 PM, Jaehoon Chung  wrote:
> Hi Vivek,
>
> On 12/28/2016 05:58 PM, Vivek Gautam wrote:
>> Hi Jaehoon,
>>
>> On Wed, Dec 28, 2016 at 8:19 AM, Jaehoon Chung  
>> wrote:
>>> Hi Vivek,
>>>
>>> On 12/27/2016 02:53 PM, Vivek Gautam wrote:
 Hi Jaehoon,


 On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung  
 wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
>
> Signed-off-by: Jaehoon Chung 
> ---
>  drivers/phy/Kconfig   |   9 ++
>  drivers/phy/Makefile  |   1 +
>  drivers/phy/phy-exynos-pcie.c | 227 
> ++
>  3 files changed, 237 insertions(+)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index fe00f91..94b0433 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>   This driver provides PHY interface for USB 3.0 DRD controller
>   present on Exynos5 SoC series.
>
> +config PHY_EXYNOS_PCIE
> +   bool "Exynos PCIe PHY driver"

 Is there a reason for this not being 'tristate' ?
>>>
>>> Will change.
>>
>> I notice that PCI_EXYNOS5433 is bool as well.
>> If the host has to be 'bool' then it makes sense to have phy
>> also bool as well. But if PCI_EXYNOS5433 can be made
>> tristate, then this also changes to tristate.
>
> Right. I understood what you said.
>
>>
>>>

> +   depends on ARCH_EXYNOS && OF
> +   depends on PCI_EXYNOS5433
> +   select GENERIC_PHY
> +   help
> + Enable PCIe PHY support for Exynos SoC series.

 If this driver is for Exynos5433, then same should come in this help
 text as well.
>>>
>>> will support the other exynos series.
>>> I'm working on refactoring exynos5440 with PHY generic Framework.
>>> Then this drive is not for only Exnyos5433. how about?
>>
>> Ok, it's good then. My only concern is 'depends on PCI_EXYNOS5433'
>> makes it look like it is for EXYNOS5433. I am fine if that changes as well.
>
> I will not put PCI_EXYNOS5433, just will use the PCI_EXYNOS.
> Because it will be supported only one file as pci-exynos.c

cool then.

[...]

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

Hi Vivek,

On 12/28/2016 05:58 PM, Vivek Gautam wrote:
> Hi Jaehoon,
> 
> On Wed, Dec 28, 2016 at 8:19 AM, Jaehoon Chung  wrote:
>> Hi Vivek,
>>
>> On 12/27/2016 02:53 PM, Vivek Gautam wrote:
>>> Hi Jaehoon,
>>>
>>>
>>> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung  
>>> wrote:
 This patch supports to use Generic Phy framework for Exynos PCIe phy.
 When Exynos that supported the pcie want to use the PCIe,
 it needs to control the phy resgister.
 But it should be more complex to control in their own PCIe device drivers.

 Signed-off-by: Jaehoon Chung 
 ---
  drivers/phy/Kconfig   |   9 ++
  drivers/phy/Makefile  |   1 +
  drivers/phy/phy-exynos-pcie.c | 227 
 ++
  3 files changed, 237 insertions(+)
  create mode 100644 drivers/phy/phy-exynos-pcie.c

 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
 index fe00f91..94b0433 100644
 --- a/drivers/phy/Kconfig
 +++ b/drivers/phy/Kconfig
 @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
   This driver provides PHY interface for USB 3.0 DRD controller
   present on Exynos5 SoC series.

 +config PHY_EXYNOS_PCIE
 +   bool "Exynos PCIe PHY driver"
>>>
>>> Is there a reason for this not being 'tristate' ?
>>
>> Will change.
> 
> I notice that PCI_EXYNOS5433 is bool as well.
> If the host has to be 'bool' then it makes sense to have phy
> also bool as well. But if PCI_EXYNOS5433 can be made
> tristate, then this also changes to tristate.

Right. I understood what you said.

> 
>>
>>>
 +   depends on ARCH_EXYNOS && OF
 +   depends on PCI_EXYNOS5433
 +   select GENERIC_PHY
 +   help
 + Enable PCIe PHY support for Exynos SoC series.
>>>
>>> If this driver is for Exynos5433, then same should come in this help
>>> text as well.
>>
>> will support the other exynos series.
>> I'm working on refactoring exynos5440 with PHY generic Framework.
>> Then this drive is not for only Exnyos5433. how about?
> 
> Ok, it's good then. My only concern is 'depends on PCI_EXYNOS5433'
> makes it look like it is for EXYNOS5433. I am fine if that changes as well.

I will not put PCI_EXYNOS5433, just will use the PCI_EXYNOS.
Because it will be supported only one file as pci-exynos.c

> 
> [...]
> 
 +
 +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
 +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
 +
 +/* Sysreg Fsys register offset and bit for Exynos5433 */
 +#define PCIE_PHY_MAC_RESET 0x208
 +#define PCIE_MAC_RESET_MASK0xFF
 +#define PCIE_MAC_RESET BIT(4)
 +#define PCIE_L1SUB_CM_CON  0x1010
 +#define PCIE_REFCLK_GATING_EN  BIT(0)
 +#define PCIE_PHY_COMMON_RESET  0x1020
 +#define PCIE_PHY_RESET BIT(0)
 +#define PCIE_PHY_GLOBAL_RESET  0x1040
 +#define PCIE_GLOBAL_RESET  BIT(0)
 +#define PCIE_REFCLKBIT(1)
 +#define PCIE_REFCLK_MASK   0x16
 +#define PCIE_APP_REQ_EXIT_L1_MODE  BIT(5)
 +
 +enum exynos_pcie_phy_data_type {
 +   PCIE_PHY_TYPE_EXYNOS5433,
 +};
 +
 +struct exynos_pcie_phy_data {
 +   enum exynos_pcie_phy_data_type  ctrl_type;
>>>
>>> Why do we need this controller type ?
>>> If there are changes in the IP between different version,
>>> then you can as well use different compatibles.
>>
>> Do you mean is the using "of_device_is_compatible()"?
> 
> I meant that multiple compatible strings can be added based on the
> IP versions. And any IP specific data can be put in the .data field
> of  'of_device_id' structure.
> If there's more to differentiate between the IP versions at runtime,
> you can use of_device_is_compatible().
> 
> [...]
> 
> 
> 

Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy

[Vivek Gautam]

Hi Jaehoon,

On Wed, Dec 28, 2016 at 8:19 AM, Jaehoon Chung  wrote:
> Hi Vivek,
>
> On 12/27/2016 02:53 PM, Vivek Gautam wrote:
>> Hi Jaehoon,
>>
>>
>> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung  
>> wrote:
>>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>>> When Exynos that supported the pcie want to use the PCIe,
>>> it needs to control the phy resgister.
>>> But it should be more complex to control in their own PCIe device drivers.
>>>
>>> Signed-off-by: Jaehoon Chung 
>>> ---
>>>  drivers/phy/Kconfig   |   9 ++
>>>  drivers/phy/Makefile  |   1 +
>>>  drivers/phy/phy-exynos-pcie.c | 227 
>>> ++
>>>  3 files changed, 237 insertions(+)
>>>  create mode 100644 drivers/phy/phy-exynos-pcie.c
>>>
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index fe00f91..94b0433 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>>>   This driver provides PHY interface for USB 3.0 DRD controller
>>>   present on Exynos5 SoC series.
>>>
>>> +config PHY_EXYNOS_PCIE
>>> +   bool "Exynos PCIe PHY driver"
>>
>> Is there a reason for this not being 'tristate' ?
>
> Will change.

I notice that PCI_EXYNOS5433 is bool as well.
If the host has to be 'bool' then it makes sense to have phy
also bool as well. But if PCI_EXYNOS5433 can be made
tristate, then this also changes to tristate.

>
>>
>>> +   depends on ARCH_EXYNOS && OF
>>> +   depends on PCI_EXYNOS5433
>>> +   select GENERIC_PHY
>>> +   help
>>> + Enable PCIe PHY support for Exynos SoC series.
>>
>> If this driver is for Exynos5433, then same should come in this help
>> text as well.
>
> will support the other exynos series.
> I'm working on refactoring exynos5440 with PHY generic Framework.
> Then this drive is not for only Exnyos5433. how about?

Ok, it's good then. My only concern is 'depends on PCI_EXYNOS5433'
makes it look like it is for EXYNOS5433. I am fine if that changes as well.

[...]

>>> +
>>> +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
>>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>>> +
>>> +/* Sysreg Fsys register offset and bit for Exynos5433 */
>>> +#define PCIE_PHY_MAC_RESET 0x208
>>> +#define PCIE_MAC_RESET_MASK0xFF
>>> +#define PCIE_MAC_RESET BIT(4)
>>> +#define PCIE_L1SUB_CM_CON  0x1010
>>> +#define PCIE_REFCLK_GATING_EN  BIT(0)
>>> +#define PCIE_PHY_COMMON_RESET  0x1020
>>> +#define PCIE_PHY_RESET BIT(0)
>>> +#define PCIE_PHY_GLOBAL_RESET  0x1040
>>> +#define PCIE_GLOBAL_RESET  BIT(0)
>>> +#define PCIE_REFCLKBIT(1)
>>> +#define PCIE_REFCLK_MASK   0x16
>>> +#define PCIE_APP_REQ_EXIT_L1_MODE  BIT(5)
>>> +
>>> +enum exynos_pcie_phy_data_type {
>>> +   PCIE_PHY_TYPE_EXYNOS5433,
>>> +};
>>> +
>>> +struct exynos_pcie_phy_data {
>>> +   enum exynos_pcie_phy_data_type  ctrl_type;
>>
>> Why do we need this controller type ?
>> If there are changes in the IP between different version,
>> then you can as well use different compatibles.
>
> Do you mean is the using "of_device_is_compatible()"?

I meant that multiple compatible strings can be added based on the
IP versions. And any IP specific data can be put in the .data field
of  'of_device_id' structure.
If there's more to differentiate between the IP versions at runtime,
you can use of_device_is_compatible().

[...]



-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

Hi Vivek,

On 12/27/2016 02:53 PM, Vivek Gautam wrote:
> Hi Jaehoon,
> 
> 
> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung  
> wrote:
>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>> When Exynos that supported the pcie want to use the PCIe,
>> it needs to control the phy resgister.
>> But it should be more complex to control in their own PCIe device drivers.
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>>  drivers/phy/Kconfig   |   9 ++
>>  drivers/phy/Makefile  |   1 +
>>  drivers/phy/phy-exynos-pcie.c | 227 
>> ++
>>  3 files changed, 237 insertions(+)
>>  create mode 100644 drivers/phy/phy-exynos-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index fe00f91..94b0433 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>>   This driver provides PHY interface for USB 3.0 DRD controller
>>   present on Exynos5 SoC series.
>>
>> +config PHY_EXYNOS_PCIE
>> +   bool "Exynos PCIe PHY driver"
> 
> Is there a reason for this not being 'tristate' ?

Will change.

> 
>> +   depends on ARCH_EXYNOS && OF
>> +   depends on PCI_EXYNOS5433
>> +   select GENERIC_PHY
>> +   help
>> + Enable PCIe PHY support for Exynos SoC series.
> 
> If this driver is for Exynos5433, then same should come in this help
> text as well.

will support the other exynos series.
I'm working on refactoring exynos5440 with PHY generic Framework.
Then this drive is not for only Exnyos5433. how about?

> 
>> + This driver provides PHY interface for Exynos PCIe controller.
>> +
>>  config PHY_PISTACHIO_USB
>> tristate "IMG Pistachio USB2.0 PHY driver"
>> depends on MACH_PISTACHIO
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a534cf5..586344d 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -38,6 +38,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
>> phy-exynos4x12-usb2.o
>>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
>>  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
>>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
>> +obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
>>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
>>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
>> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
>> new file mode 100644
>> index 000..0f5eefd
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-pcie.c
>> @@ -0,0 +1,227 @@
>> +/*
>> + * Samsung EXYNOS SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on Exynos SoC series
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
>> + * Jaehoon Chung 
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
> 
> nit: It's good to have these includes in alphabetical order.

Will fix.

> 
>> +
>> +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>> +
>> +/* Sysreg Fsys register offset and bit for Exynos5433 */
>> +#define PCIE_PHY_MAC_RESET 0x208
>> +#define PCIE_MAC_RESET_MASK0xFF
>> +#define PCIE_MAC_RESET BIT(4)
>> +#define PCIE_L1SUB_CM_CON  0x1010
>> +#define PCIE_REFCLK_GATING_EN  BIT(0)
>> +#define PCIE_PHY_COMMON_RESET  0x1020
>> +#define PCIE_PHY_RESET BIT(0)
>> +#define PCIE_PHY_GLOBAL_RESET  0x1040
>> +#define PCIE_GLOBAL_RESET  BIT(0)
>> +#define PCIE_REFCLKBIT(1)
>> +#define PCIE_REFCLK_MASK   0x16
>> +#define PCIE_APP_REQ_EXIT_L1_MODE  BIT(5)
>> +
>> +enum exynos_pcie_phy_data_type {
>> +   PCIE_PHY_TYPE_EXYNOS5433,
>> +};
>> +
>> +struct exynos_pcie_phy_data {
>> +   enum exynos_pcie_phy_data_type  ctrl_type;
> 
> Why do we need this controller type ?
> If there are changes in the IP between different version,
> then you can as well use different compatibles.

Do you mean is the using "of_device_is_compatible()"?

> 
>> +   u32 pmureg_offset; /* PMU_REG offset */
> 
> Please use top comments.
> 
>> +   struct phy_ops  *ops;
>> +};
>> +
>> +/* for Exynos pcie phy */
>> +struct exynos_pcie_phy {
>> +   const struct exynos_pcie_phy_data *drv_data;
>> +   struct regmap *pmureg;
>> +   struct regmap *fsysreg;
>> +   void __iomem *phy_base;
> 
> just 'base' ?

Will change

> 
>> +};
>> +
>> +static void exynos_pcie_phy_writel(void __iomem *base

Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy

[Vivek Gautam]

Hi Jaehoon,


On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung  wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
>
> Signed-off-by: Jaehoon Chung 
> ---
>  drivers/phy/Kconfig   |   9 ++
>  drivers/phy/Makefile  |   1 +
>  drivers/phy/phy-exynos-pcie.c | 227 
> ++
>  3 files changed, 237 insertions(+)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index fe00f91..94b0433 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>   This driver provides PHY interface for USB 3.0 DRD controller
>   present on Exynos5 SoC series.
>
> +config PHY_EXYNOS_PCIE
> +   bool "Exynos PCIe PHY driver"

Is there a reason for this not being 'tristate' ?

> +   depends on ARCH_EXYNOS && OF
> +   depends on PCI_EXYNOS5433
> +   select GENERIC_PHY
> +   help
> + Enable PCIe PHY support for Exynos SoC series.

If this driver is for Exynos5433, then same should come in this help
text as well.

> + This driver provides PHY interface for Exynos PCIe controller.
> +
>  config PHY_PISTACHIO_USB
> tristate "IMG Pistachio USB2.0 PHY driver"
> depends on MACH_PISTACHIO
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a534cf5..586344d 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -38,6 +38,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
> phy-exynos4x12-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
> +obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> new file mode 100644
> index 000..0f5eefd
> --- /dev/null
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -0,0 +1,227 @@
> +/*
> + * Samsung EXYNOS SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on Exynos SoC series
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> + * Jaehoon Chung 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 

nit: It's good to have these includes in alphabetical order.

> +
> +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
> +
> +/* Sysreg Fsys register offset and bit for Exynos5433 */
> +#define PCIE_PHY_MAC_RESET 0x208
> +#define PCIE_MAC_RESET_MASK0xFF
> +#define PCIE_MAC_RESET BIT(4)
> +#define PCIE_L1SUB_CM_CON  0x1010
> +#define PCIE_REFCLK_GATING_EN  BIT(0)
> +#define PCIE_PHY_COMMON_RESET  0x1020
> +#define PCIE_PHY_RESET BIT(0)
> +#define PCIE_PHY_GLOBAL_RESET  0x1040
> +#define PCIE_GLOBAL_RESET  BIT(0)
> +#define PCIE_REFCLKBIT(1)
> +#define PCIE_REFCLK_MASK   0x16
> +#define PCIE_APP_REQ_EXIT_L1_MODE  BIT(5)
> +
> +enum exynos_pcie_phy_data_type {
> +   PCIE_PHY_TYPE_EXYNOS5433,
> +};
> +
> +struct exynos_pcie_phy_data {
> +   enum exynos_pcie_phy_data_type  ctrl_type;

Why do we need this controller type ?
If there are changes in the IP between different version,
then you can as well use different compatibles.

> +   u32 pmureg_offset; /* PMU_REG offset */

Please use top comments.

> +   struct phy_ops  *ops;
> +};
> +
> +/* for Exynos pcie phy */
> +struct exynos_pcie_phy {
> +   const struct exynos_pcie_phy_data *drv_data;
> +   struct regmap *pmureg;
> +   struct regmap *fsysreg;
> +   void __iomem *phy_base;

just 'base' ?

> +};
> +
> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
> +{
> +   writel(val, base + offset);
> +}
> +
> +static int exynos_pcie_phy_init(struct phy *phy)
> +{
> +   struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> +   if (ep->fsysreg) {
> +   regmap_update_bits(ep->fsysreg, PCIE_PHY_COMMON_RESET,
> +   PCIE_PHY_RESET, 1);
> +   regmap_update_bits(ep->fsysreg, PCIE_PHY_MAC_RESET,
> +   PCIE_MAC_RESET, 0);
> 

[RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

This patch supports to use Generic Phy framework for Exynos PCIe phy.
When Exynos that supported the pcie want to use the PCIe,
it needs to control the phy resgister.
But it should be more complex to control in their own PCIe device drivers.

Signed-off-by: Jaehoon Chung 
---
 drivers/phy/Kconfig   |   9 ++
 drivers/phy/Makefile  |   1 +
 drivers/phy/phy-exynos-pcie.c | 227 ++
 3 files changed, 237 insertions(+)
 create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index fe00f91..94b0433 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
  This driver provides PHY interface for USB 3.0 DRD controller
  present on Exynos5 SoC series.
 
+config PHY_EXYNOS_PCIE
+   bool "Exynos PCIe PHY driver"
+   depends on ARCH_EXYNOS && OF
+   depends on PCI_EXYNOS5433
+   select GENERIC_PHY
+   help
+ Enable PCIe PHY support for Exynos SoC series.
+ This driver provides PHY interface for Exynos PCIe controller.
+
 config PHY_PISTACHIO_USB
tristate "IMG Pistachio USB2.0 PHY driver"
depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a534cf5..586344d 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,6 +38,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 000..0f5eefd
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,227 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
+#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
+
+/* Sysreg Fsys register offset and bit for Exynos5433 */
+#define PCIE_PHY_MAC_RESET 0x208
+#define PCIE_MAC_RESET_MASK0xFF
+#define PCIE_MAC_RESET BIT(4)
+#define PCIE_L1SUB_CM_CON  0x1010
+#define PCIE_REFCLK_GATING_EN  BIT(0)
+#define PCIE_PHY_COMMON_RESET  0x1020
+#define PCIE_PHY_RESET BIT(0)
+#define PCIE_PHY_GLOBAL_RESET  0x1040
+#define PCIE_GLOBAL_RESET  BIT(0)
+#define PCIE_REFCLKBIT(1)
+#define PCIE_REFCLK_MASK   0x16
+#define PCIE_APP_REQ_EXIT_L1_MODE  BIT(5)
+
+enum exynos_pcie_phy_data_type {
+   PCIE_PHY_TYPE_EXYNOS5433,
+};
+
+struct exynos_pcie_phy_data {
+   enum exynos_pcie_phy_data_type  ctrl_type;
+   u32 pmureg_offset; /* PMU_REG offset */
+   struct phy_ops  *ops;
+};
+
+/* for Exynos pcie phy */
+struct exynos_pcie_phy {
+   const struct exynos_pcie_phy_data *drv_data;
+   struct regmap *pmureg;
+   struct regmap *fsysreg;
+   void __iomem *phy_base;
+};
+
+static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
+{
+   writel(val, base + offset);
+}
+
+static int exynos_pcie_phy_init(struct phy *phy)
+{
+   struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+
+   if (ep->fsysreg) {
+   regmap_update_bits(ep->fsysreg, PCIE_PHY_COMMON_RESET,
+   PCIE_PHY_RESET, 1);
+   regmap_update_bits(ep->fsysreg, PCIE_PHY_MAC_RESET,
+   PCIE_MAC_RESET, 0);
+   /* PHY refclk 24MHz */
+   regmap_update_bits(ep->fsysreg, PCIE_PHY_GLOBAL_RESET,
+   PCIE_REFCLK_MASK, PCIE_REFCLK);
+   regmap_update_bits(ep->fsysreg, PCIE_PHY_GLOBAL_RESET,
+   PCIE_GLOBAL_RESET, 0);
+   }
+
+   exynos_pcie_phy_writel(ep->phy_base, 0x11, PCIE_PHY_OFFSET(0x3));
+
+   /* band gap reference on */
+   exynos_pcie_phy_writel(ep->phy_base, 0, PCIE_PHY_OFFSET(0x20));
+   exynos_pcie_phy_writel(ep->phy_base, 0, PCIE_PHY_OFFSET(0x4b));
+
+   /* jitter tunning */
+   exynos_pcie_phy_writel(ep->phy_base, 0x34, PCIE_PHY_OFFSET(0x4));
+   exynos_pcie_phy_writel(ep->ph