Re: [RFC part2 PATCH 8/9] ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ subsystem

2014-01-20 Thread Grant Likely 
On Wed, 11 Dec 2013 06:23:04 +0100, Arnd Bergmann  wrote:
> On Tuesday 10 December 2013, Grant Likely wrote:
> > > --- a/drivers/acpi/plat/arm-core.c
> > > +++ b/drivers/acpi/plat/arm-core.c
> > > @@ -90,7 +90,7 @@ enum acpi_irq_model_id acpi_irq_model = 
> > > ACPI_IRQ_MODEL_GIC;
> > >  
> > >  static unsigned int gsi_to_irq(unsigned int gsi)
> > >  {
> > > - int irq = irq_create_mapping(NULL, gsi);
> > > + int irq = irq_find_mapping(NULL, gsi);
> > 
> > I suspect this will break FDT users that depend on the old behaviour.
> 
> I think not, given this is only in drivers/acpi and gets added in one
> of the prior patches of the same series.

Ah, okay.

g.

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Re: [RFC part2 PATCH 8/9] ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ subsystem

2013-12-10 Thread Arnd Bergmann 
On Tuesday 10 December 2013, Grant Likely wrote:
> > --- a/drivers/acpi/plat/arm-core.c
> > +++ b/drivers/acpi/plat/arm-core.c
> > @@ -90,7 +90,7 @@ enum acpi_irq_model_id acpi_irq_model = 
> > ACPI_IRQ_MODEL_GIC;
> >  
> >  static unsigned int gsi_to_irq(unsigned int gsi)
> >  {
> > - int irq = irq_create_mapping(NULL, gsi);
> > + int irq = irq_find_mapping(NULL, gsi);
> 
> I suspect this will break FDT users that depend on the old behaviour.

I think not, given this is only in drivers/acpi and gets added in one
of the prior patches of the same series.

Arnd
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Re: [RFC part2 PATCH 8/9] ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ subsystem

2013-12-10 Thread Grant Likely 
On Mon,  2 Dec 2013 23:44:53 +0800, Hanjun Guo  wrote:
> This API is similar to DT based irq_of_parse_and_map but does link
> parent/child IRQ controllers. This is tested for primary GIC PPI and GIC SPI
> interrupts and not for secondary child irq controllers.
> 
> Signed-off-by: Amit Daniel Kachhap 
> Signed-off-by: Hanjun Guo 
> ---
>  drivers/acpi/plat/arm-core.c |   36 ++--
>  1 file changed, 34 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/acpi/plat/arm-core.c b/drivers/acpi/plat/arm-core.c
> index 9cc0208..17c99e1 100644
> --- a/drivers/acpi/plat/arm-core.c
> +++ b/drivers/acpi/plat/arm-core.c
> @@ -90,7 +90,7 @@ enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC;
>  
>  static unsigned int gsi_to_irq(unsigned int gsi)
>  {
> - int irq = irq_create_mapping(NULL, gsi);
> + int irq = irq_find_mapping(NULL, gsi);

I suspect this will break FDT users that depend on the old behaviour.

g.

>  
>   return irq;
>  }
> @@ -407,7 +407,39 @@ EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
>   */
>  int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
>  {
> - return -1;
> + unsigned int irq;
> + unsigned int irq_type;
> + 
> + /*
> +  * ACPI have no bindings to indicate SPI or PPI, so we
> +  * use different mappings from DT in ACPI.
> +  *
> +  * For FDT
> +  * PPI interrupt: in the range [0, 15];
> +  * SPI interrupt: in the range [0, 987];
> +  *
> +  * For ACPI, using identity mapping for hwirq:
> +  * PPI interrupt: in the range [16, 31];
> +  * SPI interrupt: in the range [32, 1019];
> +  */
> +
> + if (trigger == ACPI_EDGE_SENSITIVE &&
> + polarity == ACPI_ACTIVE_LOW)
> + irq_type = IRQ_TYPE_EDGE_FALLING;
> + else if (trigger == ACPI_EDGE_SENSITIVE &&
> + polarity == ACPI_ACTIVE_HIGH)
> + irq_type = IRQ_TYPE_EDGE_RISING;
> + else if (trigger == ACPI_LEVEL_SENSITIVE &&
> + polarity == ACPI_ACTIVE_LOW)
> + irq_type = IRQ_TYPE_LEVEL_LOW;
> + else if (trigger == ACPI_LEVEL_SENSITIVE &&
> + polarity == ACPI_ACTIVE_HIGH)
> + irq_type = IRQ_TYPE_LEVEL_HIGH;
> + else
> + irq_type = IRQ_TYPE_NONE;
> +
> + irq = irq_create_acpi_mapping(gsi, irq_type);
> + return irq; 
>  }
>  EXPORT_SYMBOL_GPL(acpi_register_gsi);
>  
> -- 
> 1.7.9.5
> 
> 
> ___
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Re: [RFC part2 PATCH 8/9] ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ subsystem

2013-12-05 Thread Hanjun Guo 

On 2013年12月05日 11:48, Arnd Bergmann wrote:

On Tuesday 03 December 2013, Hanjun Guo wrote:

+   /*
+* ACPI have no bindings to indicate SPI or PPI, so we
+* use different mappings from DT in ACPI.
+*
+* For FDT
+* PPI interrupt: in the range [0, 15];
+* SPI interrupt: in the range [0, 987];
+*
+* For ACPI, using identity mapping for hwirq:
+* PPI interrupt: in the range [16, 31];
+* SPI interrupt: in the range [32, 1019];

This difference might cause endless confusion. Can't you register PPI and SPI as
separate IRQ controllers to have the same number space that we normally have?


In ACPI, they used a conception named GSI (Global System Interrupts)
for irq, GSI number can not be the same even if there are muti GICs,
so I use the identity mapping for hwirq for ACPI.

Thanks you very much for your comments :)

Hanjun
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Re: [RFC part2 PATCH 8/9] ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ subsystem

2013-12-04 Thread Arnd Bergmann 
On Tuesday 03 December 2013, Hanjun Guo wrote:
> +   /*
> +* ACPI have no bindings to indicate SPI or PPI, so we
> +* use different mappings from DT in ACPI.
> +*
> +* For FDT
> +* PPI interrupt: in the range [0, 15];
> +* SPI interrupt: in the range [0, 987];
> +*
> +* For ACPI, using identity mapping for hwirq:
> +* PPI interrupt: in the range [16, 31];
> +* SPI interrupt: in the range [32, 1019];

This difference might cause endless confusion. Can't you register PPI and SPI as
separate IRQ controllers to have the same number space that we normally have?

Arnd
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[RFC part2 PATCH 8/9] ACPI / ARM64: Update acpi_register_gsi to register with the core IRQ subsystem

2013-12-03 Thread Hanjun Guo 
This API is similar to DT based irq_of_parse_and_map but does link
parent/child IRQ controllers. This is tested for primary GIC PPI and GIC SPI
interrupts and not for secondary child irq controllers.

Signed-off-by: Amit Daniel Kachhap 
Signed-off-by: Hanjun Guo 
---
 drivers/acpi/plat/arm-core.c |   36 ++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/acpi/plat/arm-core.c b/drivers/acpi/plat/arm-core.c
index 9cc0208..17c99e1 100644
--- a/drivers/acpi/plat/arm-core.c
+++ b/drivers/acpi/plat/arm-core.c
@@ -90,7 +90,7 @@ enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC;
 
 static unsigned int gsi_to_irq(unsigned int gsi)
 {
-   int irq = irq_create_mapping(NULL, gsi);
+   int irq = irq_find_mapping(NULL, gsi);
 
return irq;
 }
@@ -407,7 +407,39 @@ EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
  */
 int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
 {
-   return -1;
+   unsigned int irq;
+   unsigned int irq_type;
+ 
+   /*
+* ACPI have no bindings to indicate SPI or PPI, so we
+* use different mappings from DT in ACPI.
+*
+* For FDT
+* PPI interrupt: in the range [0, 15];
+* SPI interrupt: in the range [0, 987];
+*
+* For ACPI, using identity mapping for hwirq:
+* PPI interrupt: in the range [16, 31];
+* SPI interrupt: in the range [32, 1019];
+*/
+
+   if (trigger == ACPI_EDGE_SENSITIVE &&
+   polarity == ACPI_ACTIVE_LOW)
+   irq_type = IRQ_TYPE_EDGE_FALLING;
+   else if (trigger == ACPI_EDGE_SENSITIVE &&
+   polarity == ACPI_ACTIVE_HIGH)
+   irq_type = IRQ_TYPE_EDGE_RISING;
+   else if (trigger == ACPI_LEVEL_SENSITIVE &&
+   polarity == ACPI_ACTIVE_LOW)
+   irq_type = IRQ_TYPE_LEVEL_LOW;
+   else if (trigger == ACPI_LEVEL_SENSITIVE &&
+   polarity == ACPI_ACTIVE_HIGH)
+   irq_type = IRQ_TYPE_LEVEL_HIGH;
+   else
+   irq_type = IRQ_TYPE_NONE;
+
+   irq = irq_create_acpi_mapping(gsi, irq_type);
+   return irq; 
 }
 EXPORT_SYMBOL_GPL(acpi_register_gsi);
 
-- 
1.7.9.5

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