Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU

2020-12-10 Thread André Przywara 
On 10/12/2020 13:31, Icenowy Zheng wrote:
> 在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
>> While the clocks are fairly similar to the H6, many differ in tiny
>> details, so a separate clock driver seems indicated.
>>
>> Derived from the H6 clock driver, and adjusted according to the
>> manual.
>>
>> Signed-off-by: Andre Przywara 
>> ---
>>  drivers/clk/sunxi-ng/Kconfig|7 +-
>>  drivers/clk/sunxi-ng/Makefile   |1 +
>>  drivers/clk/sunxi-ng/ccu-sun50i-h616.c  | 1134
>> +++
>>  drivers/clk/sunxi-ng/ccu-sun50i-h616.h  |   58 +
>>  include/dt-bindings/clock/sun50i-h616-ccu.h |  110 ++
>>  include/dt-bindings/reset/sun50i-h616-ccu.h |   67 ++
>>  6 files changed, 1376 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
>>  create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
>>  create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
>>
>> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-
>> ng/Kconfig
>> index ce5f5847d5d3..cd46d8853876 100644
>> --- a/drivers/clk/sunxi-ng/Kconfig
>> +++ b/drivers/clk/sunxi-ng/Kconfig
>> @@ -32,8 +32,13 @@ config SUN50I_H6_CCU
>>  default ARM64 && ARCH_SUNXI
>>  depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>>  
>> +config SUN50I_H616_CCU
>> +bool "Support for the Allwinner H616 CCU"
>> +default ARM64 && ARCH_SUNXI
>> +depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>> +
>>  config SUN50I_H6_R_CCU
>> -bool "Support for the Allwinner H6 PRCM CCU"
>> +bool "Support for the Allwinner H6 and H616 PRCM CCU"
>>  default ARM64 && ARCH_SUNXI
>>  depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>>  
>> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-
>> ng/Makefile
>> index 3eb5cff40eac..96c324306d97 100644
>> --- a/drivers/clk/sunxi-ng/Makefile
>> +++ b/drivers/clk/sunxi-ng/Makefile
>> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU)   += ccu-sun50i-
>> a64.o
>>  obj-$(CONFIG_SUN50I_A100_CCU)   += ccu-sun50i-a100.o
>>  obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
>>  obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
>> +obj-$(CONFIG_SUN50I_H616_CCU)   += ccu-sun50i-h616.o
>>  obj-$(CONFIG_SUN50I_H6_R_CCU)   += ccu-sun50i-h6-r.o
>>  obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
>>  obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> new file mode 100644
>> index ..3fbb258f0354
>> --- /dev/null
>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> @@ -0,0 +1,1134 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2020 Arm Ltd.
>> + * Based on the H6 CCU driver, which is:
>> + *   Copyright (c) 2017 Icenowy Zheng 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "ccu_common.h"
>> +#include "ccu_reset.h"
>> +
>> +#include "ccu_div.h"
>> +#include "ccu_gate.h"
>> +#include "ccu_mp.h"
>> +#include "ccu_mult.h"
>> +#include "ccu_nk.h"
>> +#include "ccu_nkm.h"
>> +#include "ccu_nkmp.h"
>> +#include "ccu_nm.h"
>> +
>> +#include "ccu-sun50i-h616.h"
>> +
>> +/*
>> + * The CPU PLL is actually NP clock, with P being /1, /2 or /4.
>> However
>> + * P should only be used for output frequencies lower than 288 MHz.
>> + *
>> + * For now we can just model it as a multiplier clock, and force P
>> to /1.
>> + *
>> + * The M factor is present in the register's description, but not in
>> the
>> + * frequency formula, and it's documented as "M is only used for
>> backdoor
>> + * testing", so it's not modelled and then force to 0.
>> + */
>> +#define SUN50I_H616_PLL_CPUX_REG0x000
>> +static struct ccu_mult pll_cpux_clk = {
>> +.enable = BIT(31),
>> +.lock   = BIT(28),
>> +.mult   = _SUNXI_CCU_MULT_MIN(8, 8, 12),
>> +.common = {
>> +.reg= 0x000,
>> +.hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
>> +  _mult_ops,
>> +  CLK_SET_RATE_UNGATE),
>> +},
>> +};
>> +
>> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K
>> */
>> +#define SUN50I_H616_PLL_DDR0_REG0x010
>> +static struct ccu_nkmp pll_ddr0_clk = {
>> +.enable = BIT(31),
>> +.lock   = BIT(28),
>> +.n  = _SUNXI_CCU_MULT_MIN(8, 8, 12),
>> +.m  = _SUNXI_CCU_DIV(1, 1), /* input divider */
>> +.p  = _SUNXI_CCU_DIV(0, 1), /* output divider */
>> +.common = {
>> +.reg= 0x010,
>> +.hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
>> +  _nkmp_ops,
>> +  CLK_SET_RATE_UNGATE),
>> +},
>> +};
>> +
>> +#define SUN50I_H616_PLL_DDR1_REG

Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU

2020-12-10 Thread Icenowy Zheng 
在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
> While the clocks are fairly similar to the H6, many differ in tiny
> details, so a separate clock driver seems indicated.
> 
> Derived from the H6 clock driver, and adjusted according to the
> manual.
> 
> Signed-off-by: Andre Przywara 
> ---
>  drivers/clk/sunxi-ng/Kconfig|7 +-
>  drivers/clk/sunxi-ng/Makefile   |1 +
>  drivers/clk/sunxi-ng/ccu-sun50i-h616.c  | 1134
> +++
>  drivers/clk/sunxi-ng/ccu-sun50i-h616.h  |   58 +
>  include/dt-bindings/clock/sun50i-h616-ccu.h |  110 ++
>  include/dt-bindings/reset/sun50i-h616-ccu.h |   67 ++
>  6 files changed, 1376 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
>  create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
> 
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-
> ng/Kconfig
> index ce5f5847d5d3..cd46d8853876 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -32,8 +32,13 @@ config SUN50I_H6_CCU
>   default ARM64 && ARCH_SUNXI
>   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>  
> +config SUN50I_H616_CCU
> + bool "Support for the Allwinner H616 CCU"
> + default ARM64 && ARCH_SUNXI
> + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> +
>  config SUN50I_H6_R_CCU
> - bool "Support for the Allwinner H6 PRCM CCU"
> + bool "Support for the Allwinner H6 and H616 PRCM CCU"
>   default ARM64 && ARCH_SUNXI
>   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>  
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-
> ng/Makefile
> index 3eb5cff40eac..96c324306d97 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU)+= ccu-sun50i-
> a64.o
>  obj-$(CONFIG_SUN50I_A100_CCU)+= ccu-sun50i-a100.o
>  obj-$(CONFIG_SUN50I_A100_R_CCU)  += ccu-sun50i-a100-r.o
>  obj-$(CONFIG_SUN50I_H6_CCU)  += ccu-sun50i-h6.o
> +obj-$(CONFIG_SUN50I_H616_CCU)+= ccu-sun50i-h616.o
>  obj-$(CONFIG_SUN50I_H6_R_CCU)+= ccu-sun50i-h6-r.o
>  obj-$(CONFIG_SUN4I_A10_CCU)  += ccu-sun4i-a10.o
>  obj-$(CONFIG_SUN5I_CCU)  += ccu-sun5i.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> new file mode 100644
> index ..3fbb258f0354
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020 Arm Ltd.
> + * Based on the H6 CCU driver, which is:
> + *   Copyright (c) 2017 Icenowy Zheng 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +
> +#include "ccu-sun50i-h616.h"
> +
> +/*
> + * The CPU PLL is actually NP clock, with P being /1, /2 or /4.
> However
> + * P should only be used for output frequencies lower than 288 MHz.
> + *
> + * For now we can just model it as a multiplier clock, and force P
> to /1.
> + *
> + * The M factor is present in the register's description, but not in
> the
> + * frequency formula, and it's documented as "M is only used for
> backdoor
> + * testing", so it's not modelled and then force to 0.
> + */
> +#define SUN50I_H616_PLL_CPUX_REG 0x000
> +static struct ccu_mult pll_cpux_clk = {
> + .enable = BIT(31),
> + .lock   = BIT(28),
> + .mult   = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> + .common = {
> + .reg= 0x000,
> + .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
> +   _mult_ops,
> +   CLK_SET_RATE_UNGATE),
> + },
> +};
> +
> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K
> */
> +#define SUN50I_H616_PLL_DDR0_REG 0x010
> +static struct ccu_nkmp pll_ddr0_clk = {
> + .enable = BIT(31),
> + .lock   = BIT(28),
> + .n  = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> + .m  = _SUNXI_CCU_DIV(1, 1), /* input divider */
> + .p  = _SUNXI_CCU_DIV(0, 1), /* output divider */
> + .common = {
> + .reg= 0x010,
> + .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
> +   _nkmp_ops,
> +   CLK_SET_RATE_UNGATE),
> + },
> +};
> +
> +#define SUN50I_H616_PLL_DDR1_REG 0x018
> +static struct ccu_nkmp pll_ddr1_clk = {
> + .enable = BIT(31),
> + .lock   = BIT(28),
> + .n

Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU

2020-12-09 Thread André Przywara 
On 09/12/2020 22:20, Jernej Škrabec wrote:
> Dne sreda, 09. december 2020 ob 22:35:51 CET je André Przywara napisal(a):
>> On 09/12/2020 14:33, Clément Péron wrote:
>>
>> Hi,
>>
>>> I try to review this, and compare against the vendor Kernel>
>>>
>>> On Wed, 2 Dec 2020 at 14:54, Andre Przywara  
> wrote:
 While the clocks are fairly similar to the H6, many differ in tiny
 details, so a separate clock driver seems indicated.

 Derived from the H6 clock driver, and adjusted according to the manual.

 Signed-off-by: Andre Przywara 
 ---

  drivers/clk/sunxi-ng/Kconfig|7 +-
  drivers/clk/sunxi-ng/Makefile   |1 +
  drivers/clk/sunxi-ng/ccu-sun50i-h616.c  | 1134 +++
  drivers/clk/sunxi-ng/ccu-sun50i-h616.h  |   58 +
  include/dt-bindings/clock/sun50i-h616-ccu.h |  110 ++
  include/dt-bindings/reset/sun50i-h616-ccu.h |   67 ++
  6 files changed, 1376 insertions(+), 1 deletion(-)
  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
  create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
  create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h

 diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
 index ce5f5847d5d3..cd46d8853876 100644
 --- a/drivers/clk/sunxi-ng/Kconfig
 +++ b/drivers/clk/sunxi-ng/Kconfig
 @@ -32,8 +32,13 @@ config SUN50I_H6_CCU

 default ARM64 && ARCH_SUNXI
 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST

 +config SUN50I_H616_CCU
 +   bool "Support for the Allwinner H616 CCU"
 +   default ARM64 && ARCH_SUNXI
 +   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 +

  config SUN50I_H6_R_CCU

 -   bool "Support for the Allwinner H6 PRCM CCU"
 +   bool "Support for the Allwinner H6 and H616 PRCM CCU"

 default ARM64 && ARCH_SUNXI
 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST

 diff --git a/drivers/clk/sunxi-ng/Makefile
 b/drivers/clk/sunxi-ng/Makefile
 index 3eb5cff40eac..96c324306d97 100644
 --- a/drivers/clk/sunxi-ng/Makefile
 +++ b/drivers/clk/sunxi-ng/Makefile
 @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU)  += ccu-sun50i-a64.o

  obj-$(CONFIG_SUN50I_A100_CCU)  += ccu-sun50i-a100.o
  obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
  obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o

 +obj-$(CONFIG_SUN50I_H616_CCU)  += ccu-sun50i-h616.o

  obj-$(CONFIG_SUN50I_H6_R_CCU)  += ccu-sun50i-h6-r.o
  obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
  obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o

 diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
 b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c new file mode 100644
 index ..3fbb258f0354
 --- /dev/null
 +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
 @@ -0,0 +1,1134 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2020 Arm Ltd.
 + * Based on the H6 CCU driver, which is:
 + *   Copyright (c) 2017 Icenowy Zheng 
 + */
 +
 +#include 
 +#include 
 +#include 
 +#include 
 +
 +#include "ccu_common.h"
 +#include "ccu_reset.h"
 +
 +#include "ccu_div.h"
 +#include "ccu_gate.h"
 +#include "ccu_mp.h"
 +#include "ccu_mult.h"
 +#include "ccu_nk.h"
 +#include "ccu_nkm.h"
 +#include "ccu_nkmp.h"
 +#include "ccu_nm.h"
 +
 +#include "ccu-sun50i-h616.h"
 +
 +/*
 + * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
 + * P should only be used for output frequencies lower than 288 MHz.
 + *
 + * For now we can just model it as a multiplier clock, and force P to
 /1.
 + *
 + * The M factor is present in the register's description, but not in the
 + * frequency formula, and it's documented as "M is only used for
 backdoor
 + * testing", so it's not modelled and then force to 0.
 + */
 +#define SUN50I_H616_PLL_CPUX_REG   0x000
 +static struct ccu_mult pll_cpux_clk = {
 +   .enable = BIT(31),
 +   .lock   = BIT(28),
 +   .mult   = _SUNXI_CCU_MULT_MIN(8, 8, 12),
 +   .common = {
 +   .reg= 0x000,
 +   .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
 + _mult_ops,
 + CLK_SET_RATE_UNGATE),
 +   },
 +};
 +
 +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
 +#define SUN50I_H616_PLL_DDR0_REG   0x010
 +static struct ccu_nkmp pll_ddr0_clk = {
 +   .enable = BIT(31),
 +   .lock   = BIT(28),
 +

Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU

2020-12-09 Thread Jernej Škrabec 
Dne sreda, 09. december 2020 ob 22:35:51 CET je André Przywara napisal(a):
> On 09/12/2020 14:33, Clément Péron wrote:
> 
> Hi,
> 
> > I try to review this, and compare against the vendor Kernel>
> > 
> > On Wed, 2 Dec 2020 at 14:54, Andre Przywara  
wrote:
> >> While the clocks are fairly similar to the H6, many differ in tiny
> >> details, so a separate clock driver seems indicated.
> >> 
> >> Derived from the H6 clock driver, and adjusted according to the manual.
> >> 
> >> Signed-off-by: Andre Przywara 
> >> ---
> >> 
> >>  drivers/clk/sunxi-ng/Kconfig|7 +-
> >>  drivers/clk/sunxi-ng/Makefile   |1 +
> >>  drivers/clk/sunxi-ng/ccu-sun50i-h616.c  | 1134 +++
> >>  drivers/clk/sunxi-ng/ccu-sun50i-h616.h  |   58 +
> >>  include/dt-bindings/clock/sun50i-h616-ccu.h |  110 ++
> >>  include/dt-bindings/reset/sun50i-h616-ccu.h |   67 ++
> >>  6 files changed, 1376 insertions(+), 1 deletion(-)
> >>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> >>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
> >>  create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
> >>  create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
> >> 
> >> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> >> index ce5f5847d5d3..cd46d8853876 100644
> >> --- a/drivers/clk/sunxi-ng/Kconfig
> >> +++ b/drivers/clk/sunxi-ng/Kconfig
> >> @@ -32,8 +32,13 @@ config SUN50I_H6_CCU
> >> 
> >> default ARM64 && ARCH_SUNXI
> >> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> >> 
> >> +config SUN50I_H616_CCU
> >> +   bool "Support for the Allwinner H616 CCU"
> >> +   default ARM64 && ARCH_SUNXI
> >> +   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> >> +
> >> 
> >>  config SUN50I_H6_R_CCU
> >> 
> >> -   bool "Support for the Allwinner H6 PRCM CCU"
> >> +   bool "Support for the Allwinner H6 and H616 PRCM CCU"
> >> 
> >> default ARM64 && ARCH_SUNXI
> >> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> >> 
> >> diff --git a/drivers/clk/sunxi-ng/Makefile
> >> b/drivers/clk/sunxi-ng/Makefile
> >> index 3eb5cff40eac..96c324306d97 100644
> >> --- a/drivers/clk/sunxi-ng/Makefile
> >> +++ b/drivers/clk/sunxi-ng/Makefile
> >> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU)  += ccu-sun50i-a64.o
> >> 
> >>  obj-$(CONFIG_SUN50I_A100_CCU)  += ccu-sun50i-a100.o
> >>  obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
> >>  obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
> >> 
> >> +obj-$(CONFIG_SUN50I_H616_CCU)  += ccu-sun50i-h616.o
> >> 
> >>  obj-$(CONFIG_SUN50I_H6_R_CCU)  += ccu-sun50i-h6-r.o
> >>  obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
> >>  obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
> >> 
> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> >> b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c new file mode 100644
> >> index ..3fbb258f0354
> >> --- /dev/null
> >> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> >> @@ -0,0 +1,1134 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (c) 2020 Arm Ltd.
> >> + * Based on the H6 CCU driver, which is:
> >> + *   Copyright (c) 2017 Icenowy Zheng 
> >> + */
> >> +
> >> +#include 
> >> +#include 
> >> +#include 
> >> +#include 
> >> +
> >> +#include "ccu_common.h"
> >> +#include "ccu_reset.h"
> >> +
> >> +#include "ccu_div.h"
> >> +#include "ccu_gate.h"
> >> +#include "ccu_mp.h"
> >> +#include "ccu_mult.h"
> >> +#include "ccu_nk.h"
> >> +#include "ccu_nkm.h"
> >> +#include "ccu_nkmp.h"
> >> +#include "ccu_nm.h"
> >> +
> >> +#include "ccu-sun50i-h616.h"
> >> +
> >> +/*
> >> + * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
> >> + * P should only be used for output frequencies lower than 288 MHz.
> >> + *
> >> + * For now we can just model it as a multiplier clock, and force P to
> >> /1.
> >> + *
> >> + * The M factor is present in the register's description, but not in the
> >> + * frequency formula, and it's documented as "M is only used for
> >> backdoor
> >> + * testing", so it's not modelled and then force to 0.
> >> + */
> >> +#define SUN50I_H616_PLL_CPUX_REG   0x000
> >> +static struct ccu_mult pll_cpux_clk = {
> >> +   .enable = BIT(31),
> >> +   .lock   = BIT(28),
> >> +   .mult   = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> >> +   .common = {
> >> +   .reg= 0x000,
> >> +   .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
> >> + _mult_ops,
> >> + CLK_SET_RATE_UNGATE),
> >> +   },
> >> +};
> >> +
> >> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
> >> +#define SUN50I_H616_PLL_DDR0_REG   0x010
> >> +static struct ccu_nkmp pll_ddr0_clk = {
> >> +   .enable = BIT(31),
> >> +   .lock   = BIT(28),
> >> +   .n  =

Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU

2020-12-09 Thread André Przywara 
On 09/12/2020 14:33, Clément Péron wrote:

Hi,

> I try to review this, and compare against the vendor Kernel>
> On Wed, 2 Dec 2020 at 14:54, Andre Przywara  wrote:
>>
>> While the clocks are fairly similar to the H6, many differ in tiny
>> details, so a separate clock driver seems indicated.
>>
>> Derived from the H6 clock driver, and adjusted according to the manual.
>>
>> Signed-off-by: Andre Przywara 
>> ---
>>  drivers/clk/sunxi-ng/Kconfig|7 +-
>>  drivers/clk/sunxi-ng/Makefile   |1 +
>>  drivers/clk/sunxi-ng/ccu-sun50i-h616.c  | 1134 +++
>>  drivers/clk/sunxi-ng/ccu-sun50i-h616.h  |   58 +
>>  include/dt-bindings/clock/sun50i-h616-ccu.h |  110 ++
>>  include/dt-bindings/reset/sun50i-h616-ccu.h |   67 ++
>>  6 files changed, 1376 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
>>  create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
>>  create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
>>
>> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
>> index ce5f5847d5d3..cd46d8853876 100644
>> --- a/drivers/clk/sunxi-ng/Kconfig
>> +++ b/drivers/clk/sunxi-ng/Kconfig
>> @@ -32,8 +32,13 @@ config SUN50I_H6_CCU
>> default ARM64 && ARCH_SUNXI
>> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>>
>> +config SUN50I_H616_CCU
>> +   bool "Support for the Allwinner H616 CCU"
>> +   default ARM64 && ARCH_SUNXI
>> +   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>> +
>>  config SUN50I_H6_R_CCU
>> -   bool "Support for the Allwinner H6 PRCM CCU"
>> +   bool "Support for the Allwinner H6 and H616 PRCM CCU"
>> default ARM64 && ARCH_SUNXI
>> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>>
>> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
>> index 3eb5cff40eac..96c324306d97 100644
>> --- a/drivers/clk/sunxi-ng/Makefile
>> +++ b/drivers/clk/sunxi-ng/Makefile
>> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU)  += ccu-sun50i-a64.o
>>  obj-$(CONFIG_SUN50I_A100_CCU)  += ccu-sun50i-a100.o
>>  obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
>>  obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
>> +obj-$(CONFIG_SUN50I_H616_CCU)  += ccu-sun50i-h616.o
>>  obj-$(CONFIG_SUN50I_H6_R_CCU)  += ccu-sun50i-h6-r.o
>>  obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
>>  obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c 
>> b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> new file mode 100644
>> index ..3fbb258f0354
>> --- /dev/null
>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>> @@ -0,0 +1,1134 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2020 Arm Ltd.
>> + * Based on the H6 CCU driver, which is:
>> + *   Copyright (c) 2017 Icenowy Zheng 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "ccu_common.h"
>> +#include "ccu_reset.h"
>> +
>> +#include "ccu_div.h"
>> +#include "ccu_gate.h"
>> +#include "ccu_mp.h"
>> +#include "ccu_mult.h"
>> +#include "ccu_nk.h"
>> +#include "ccu_nkm.h"
>> +#include "ccu_nkmp.h"
>> +#include "ccu_nm.h"
>> +
>> +#include "ccu-sun50i-h616.h"
>> +
>> +/*
>> + * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
>> + * P should only be used for output frequencies lower than 288 MHz.
>> + *
>> + * For now we can just model it as a multiplier clock, and force P to /1.
>> + *
>> + * The M factor is present in the register's description, but not in the
>> + * frequency formula, and it's documented as "M is only used for backdoor
>> + * testing", so it's not modelled and then force to 0.
>> + */
>> +#define SUN50I_H616_PLL_CPUX_REG   0x000
>> +static struct ccu_mult pll_cpux_clk = {
>> +   .enable = BIT(31),
>> +   .lock   = BIT(28),
>> +   .mult   = _SUNXI_CCU_MULT_MIN(8, 8, 12),
>> +   .common = {
>> +   .reg= 0x000,
>> +   .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
>> + _mult_ops,
>> + CLK_SET_RATE_UNGATE),
>> +   },
>> +};
>> +
>> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
>> +#define SUN50I_H616_PLL_DDR0_REG   0x010
>> +static struct ccu_nkmp pll_ddr0_clk = {
>> +   .enable = BIT(31),
>> +   .lock   = BIT(28),
>> +   .n  = _SUNXI_CCU_MULT_MIN(8, 8, 12),
>> +   .m  = _SUNXI_CCU_DIV(1, 1), /* input divider */
>> +   .p  = _SUNXI_CCU_DIV(0, 1), /* output divider */
>> +   .common = {
>> +   .reg= 0x010,
>> +   .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
>> + _nkmp_ops,
>> +

Re: [linux-sunxi] [PATCH 5/8] clk: sunxi-ng: Add support for the Allwinner H616 CCU

2020-12-09 Thread Clément Péron 
Hi Andre,

I try to review this, and compare against the vendor Kernel

On Wed, 2 Dec 2020 at 14:54, Andre Przywara  wrote:
>
> While the clocks are fairly similar to the H6, many differ in tiny
> details, so a separate clock driver seems indicated.
>
> Derived from the H6 clock driver, and adjusted according to the manual.
>
> Signed-off-by: Andre Przywara 
> ---
>  drivers/clk/sunxi-ng/Kconfig|7 +-
>  drivers/clk/sunxi-ng/Makefile   |1 +
>  drivers/clk/sunxi-ng/ccu-sun50i-h616.c  | 1134 +++
>  drivers/clk/sunxi-ng/ccu-sun50i-h616.h  |   58 +
>  include/dt-bindings/clock/sun50i-h616-ccu.h |  110 ++
>  include/dt-bindings/reset/sun50i-h616-ccu.h |   67 ++
>  6 files changed, 1376 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
>  create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index ce5f5847d5d3..cd46d8853876 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -32,8 +32,13 @@ config SUN50I_H6_CCU
> default ARM64 && ARCH_SUNXI
> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>
> +config SUN50I_H616_CCU
> +   bool "Support for the Allwinner H616 CCU"
> +   default ARM64 && ARCH_SUNXI
> +   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> +
>  config SUN50I_H6_R_CCU
> -   bool "Support for the Allwinner H6 PRCM CCU"
> +   bool "Support for the Allwinner H6 and H616 PRCM CCU"
> default ARM64 && ARCH_SUNXI
> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 3eb5cff40eac..96c324306d97 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU)  += ccu-sun50i-a64.o
>  obj-$(CONFIG_SUN50I_A100_CCU)  += ccu-sun50i-a100.o
>  obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
>  obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
> +obj-$(CONFIG_SUN50I_H616_CCU)  += ccu-sun50i-h616.o
>  obj-$(CONFIG_SUN50I_H6_R_CCU)  += ccu-sun50i-h6-r.o
>  obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
>  obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c 
> b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> new file mode 100644
> index ..3fbb258f0354
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020 Arm Ltd.
> + * Based on the H6 CCU driver, which is:
> + *   Copyright (c) 2017 Icenowy Zheng 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +
> +#include "ccu-sun50i-h616.h"
> +
> +/*
> + * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
> + * P should only be used for output frequencies lower than 288 MHz.
> + *
> + * For now we can just model it as a multiplier clock, and force P to /1.
> + *
> + * The M factor is present in the register's description, but not in the
> + * frequency formula, and it's documented as "M is only used for backdoor
> + * testing", so it's not modelled and then force to 0.
> + */
> +#define SUN50I_H616_PLL_CPUX_REG   0x000
> +static struct ccu_mult pll_cpux_clk = {
> +   .enable = BIT(31),
> +   .lock   = BIT(28),
> +   .mult   = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> +   .common = {
> +   .reg= 0x000,
> +   .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
> + _mult_ops,
> + CLK_SET_RATE_UNGATE),
> +   },
> +};
> +
> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
> +#define SUN50I_H616_PLL_DDR0_REG   0x010
> +static struct ccu_nkmp pll_ddr0_clk = {
> +   .enable = BIT(31),
> +   .lock   = BIT(28),
> +   .n  = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> +   .m  = _SUNXI_CCU_DIV(1, 1), /* input divider */
> +   .p  = _SUNXI_CCU_DIV(0, 1), /* output divider */
> +   .common = {
> +   .reg= 0x010,
> +   .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
> + _nkmp_ops,
> + CLK_SET_RATE_UNGATE),
> +   },
> +};
> +
> +#define SUN50I_H616_PLL_DDR1_REG   0x018
> +static struct ccu_nkmp