[patch 1/2] i2c: add master driver for mellanox systems
From: Vadim Pasternak Device driver for Mellanox I2C controller logic, implemented in Lattice CPLD device. Device supports: - Master mode - One physical bus - Polling mode The Kconfig currently controlling compilation of this code is: drivers/i2c/busses/Kconfig:config I2C_MLXCPLD Signed-off-by: Michael Shych Signed-off-by: Vadim Pasternak Reviewed-by: Jiri Pirko --- Documentation/i2c/busses/i2c-mlxcpld | 47 +++ MAINTAINERS | 9 + drivers/i2c/busses/Kconfig | 12 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-mlxcpld.c | 625 +++ 5 files changed, 694 insertions(+) create mode 100644 Documentation/i2c/busses/i2c-mlxcpld create mode 100644 drivers/i2c/busses/i2c-mlxcpld.c diff --git a/Documentation/i2c/busses/i2c-mlxcpld b/Documentation/i2c/busses/i2c-mlxcpld new file mode 100644 index 000..0f8678a --- /dev/null +++ b/Documentation/i2c/busses/i2c-mlxcpld @@ -0,0 +1,47 @@ +Driver i2c-mlxcpld + +Author: Michael Shych + +This is a for Mellanox I2C controller logic, implemented in Lattice CPLD +device. +Device supports: + - Master mode. + - One physical bus. + - Polling mode. + +This controller is equipped within the next Mellanox systems: +"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", +"msn2740", "msn2100". + +The next transaction types are supported: + - Receive Byte/Block. + - Send Byte/Block. + - Read Byte/Block. + - Write Byte/Block. + +Registers: +CTRL 0x1 - control reg. + Resets all the registers. +HALF_CYC 0x4 - cycle reg. + Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK + units). +I2C_HOLD 0x5 - hold reg. + OE (output enable) is delayed by value set to this register + (in LPC_CLK units) +CMD0x6 - command reg. + Bit 7(lsb), 0 = write, 1 = read. + Bits [6:0] - the 7bit Address of the I2C device. + It should be written last as it triggers an I2C transaction. +NUM_DATA 0x7 - data size reg. + Number of address bytes to write in read transaction +NUM_ADDR 0x8 - address reg. + Number of address bytes to write in read transaction. +STATUS 0x9 - status reg. + Bit 0 - transaction is completed. + Bit 4 - ACK/NACK. +DATAx 0xa - 0x54 - 68 bytes data buffer regs. + For write transaction address is specified in four first bytes + (DATA1 - DATA4), data starting from DATA4. + For read transactions address is send in separate transaction and + specified in four first bytes (DATA0 - DATA3). Data is reading + starting from DATA0. diff --git a/MAINTAINERS b/MAINTAINERS index 0bbe4b1..8b3f8d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7655,6 +7655,15 @@ W: http://www.mellanox.com Q: http://patchwork.ozlabs.org/project/netdev/list/ F: drivers/net/ethernet/mellanox/mlxsw/ +MELLANOX MLXCPLD I2C DRIVER +M: Vadim Pasternak +M: Michael Shych +L: linux-kernel@vger.kernel.org +S: Supported +W: http://www.mellanox.com +F: drivers/i2c/busses/i2c-mlxcpld.c +F: Documentation/i2c/busses/i2c-mlxcpld + SOFT-ROCE DRIVER (rxe) M: Moni Shoua L: linux-r...@vger.kernel.org diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 5c3993b..1126142a 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1203,4 +1203,16 @@ config I2C_OPAL This driver can also be built as a module. If so, the module will be called as i2c-opal. +config I2C_MLXCPLD +tristate "Mellanox I2C driver" +depends on X86_64 +default y +help + This exposes the Mellanox platform I2C busses to the linux I2C layer + for X86 based systems. + Controller is implemented as CPLD logic. + + This driver can also be built as a module. If so, the module will be + called as i2c-mlxcpld. + endmenu diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 37f2819..4df3578 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -118,5 +118,6 @@ obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o obj-$(CONFIG_I2C_XGENE_SLIMPRO) += i2c-xgene-slimpro.o obj-$(CONFIG_SCx200_ACB) += scx200_acb.o +obj-$(CONFIG_I2C_MLXCPLD) += i2c-mlxcpld.o ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c new file mode 100644 index 000..1ea40fa --- /dev/null +++ b/drivers/i2c/busses/i2c-mlxcpld.c @@ -0,0 +1,625 @@ +/* + * drivers/i2c/busses/i2c
Re: [patch 1/2] i2c: add master driver for mellanox systems
Hi Vadim,
[auto build test ERROR on wsa/i2c/for-next]
[also build test ERROR on v4.8-rc3 next-20160824]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
[Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for
convenience) to record what (public, well-known) commit your patch series was
built on]
[Check https://git-scm.com/docs/git-format-patch for more information]
url:
https://github.com/0day-ci/linux/commits/vadimp-mellanox-com/i2c-add-master-driver-for-mellanox-systems/20160824-200057
base: https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
i2c/for-next
config: x86_64-randconfig-s1-08242121 (attached as .config)
compiler: gcc-4.4 (Debian 4.4.7-8) 4.4.7
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/i2c/busses/i2c-mlxcpld.c: In function 'mlxcpld_i2c_lpc_write_buf':
>> drivers/i2c/busses/i2c-mlxcpld.c:148: error: implicit declaration of
>> function 'outl'
>> drivers/i2c/busses/i2c-mlxcpld.c:153: error: implicit declaration of
>> function 'outb'
drivers/i2c/busses/i2c-mlxcpld.c: In function 'mlxcpld_i2c_lpc_read_buf':
>> drivers/i2c/busses/i2c-mlxcpld.c:163: error: implicit declaration of
>> function 'inl'
>> drivers/i2c/busses/i2c-mlxcpld.c:168: error: implicit declaration of
>> function 'inb'
drivers/i2c/busses/i2c-mlxcpld.c: In function 'mlxcpld_i2c_read_comm':
>> drivers/i2c/busses/i2c-mlxcpld.c:181: error: implicit declaration of
>> function 'inw'
drivers/i2c/busses/i2c-mlxcpld.c: In function 'mlxcpld_i2c_write_comm':
>> drivers/i2c/busses/i2c-mlxcpld.c:206: error: implicit declaration of
>> function 'outw'
vim +/outl +148 drivers/i2c/busses/i2c-mlxcpld.c
142 {
143 int i, nbyte, ndword;
144
145 nbyte = len % 4;
146 ndword = len / 4;
147 for (i = 0; i < ndword; i++)
> 148 outl(*((u32 *)data + i), addr + i * 4);
149 ndword *= 4;
150 addr += ndword;
151 data += ndword;
152 for (i = 0; i < nbyte; i++)
> 153 outb(*(data + i), addr + i);
154 }
155
156 static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr)
157 {
158 int i, nbyte, ndword;
159
160 nbyte = len % 4;
161 ndword = len / 4;
162 for (i = 0; i < ndword; i++)
> 163 *((u32 *)data + i) = inl(addr + i * 4);
164 ndword *= 4;
165 addr += ndword;
166 data += ndword;
167 for (i = 0; i < nbyte; i++)
> 168 *(data + i) = inb(addr + i);
169 }
170
171 static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8
offs,
172u8 *data, u8 datalen)
173 {
174 u32 addr = priv->base_addr + offs;
175
176 switch (datalen) {
177 case 1:
178 *(data) = inb(addr);
179 break;
180 case 2:
> 181 *((u16 *)data) = inw(addr);
182 break;
183 case 3:
184 *((u16 *)data) = inw(addr);
185 *(data + 2) = inb(addr + 2);
186 break;
187 case 4:
188 *((u32 *)data) = inl(addr);
189 break;
190 default:
191 mlxcpld_i2c_lpc_read_buf(data, datalen, addr);
192 break;
193 }
194 }
195
196 static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8
offs,
197 u8 *data, u8 datalen)
198 {
199 u32 addr = priv->base_addr + offs;
200
201 switch (datalen) {
202 case 1:
203 outb(*(data), addr);
204 break;
205 case 2:
> 206 outw(*((u16 *)data), addr);
207 break;
208 case 3:
209 outw(*((u16 *)data), addr);
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: Binary data
[patch 1/2] i2c: add master driver for mellanox systems
From: Vadim Pasternak
Device driver for Mellanox I2C controller logic, implemented in Lattice CPLD
device.
Device supports:
- Master mode
- One physical bus
- Polling mode
The Kconfig currently controlling compilation of this code is:
drivers/i2c/busses/Kconfig:config I2C_MLXCPLD
Signed-off-by: Michael Shych
Signed-off-by: Vadim Pasternak
Reviewed-by: Jiri Pirko
---
drivers/i2c/busses/Kconfig | 12 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-mlxcpld.c | 609 +++
3 files changed, 622 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-mlxcpld.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 5c3993b..1126142a 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1203,4 +1203,16 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_MLXCPLD
+tristate "Mellanox I2C driver"
+depends on X86_64
+default y
+help
+ This exposes the Mellanox platform I2C busses to the linux I2C layer
+ for X86 based systems.
+ Controller is implemented as CPLD logic.
+
+ This driver can also be built as a module. If so, the module will be
+ called as i2c-mlxcpld.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 37f2819..4df3578 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -118,5 +118,6 @@ obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
obj-$(CONFIG_I2C_XGENE_SLIMPRO) += i2c-xgene-slimpro.o
obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
+obj-$(CONFIG_I2C_MLXCPLD) += i2c-mlxcpld.o
ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c
new file mode 100644
index 000..04cd987
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mlxcpld.c
@@ -0,0 +1,609 @@
+/*
+ * drivers/i2c/busses/i2c-mlxcpld.c
+ * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
+ * Copyright (c) 2016 Michael Shych
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. Neither the names of the copyright holders nor the names of its
+ *contributors may be used to endorse or promote products derived from
+ *this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* General defines */
+#define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
+#define MLXCPLD_I2C_DEVICE_NAME"mlxcpld_i2c"
+#define MLXCPLD_I2C_VALID_FLAG (I2C_M_RECV_LEN | I2C_M_RD)
+#define MLXCPLD_I2C_BUS_NUM1
+#define MLXCPLD_I2C_DATA_REG_SZ36
+#define MLXCPLD_I2C_MAX_ADDR_LEN 4
+#define MLXCPLD_I2C_RETR_NUM 2
+#define MLXCPLD_I2C_XFER_TO50 /* msec */
+#define MLXCPLD_I2C_POLL_TIME 2000 /* msec */
+
+/* LPC I2C registers */
+#define MLXCPLD_LPCI2C_LPF_REG 0x0
+#define MLXCPLD_LPCI2C_CTRL_REG0x1
+#define MLXCPLD_LPCI2C_HALF_CYC_REG0x4
+#define MLXCPLD_LPCI2C_I2C_HOLD_REG0x5
+#define MLXCPLD_LPCI2C_CMD_REG 0x6
+#define MLXCPLD_LPCI2C_NUM_DAT_REG 0x7
+#define MLXCPLD_LPCI2C_NUM_ADDR_REG0x8
+#define MLXCPLD_LPCI2C_STATUS_REG 0x9
+#define MLXCPLD_LPCI2C_DATA_REG0xa
+
+/* LPC I2C masks and parametres */
+#define MLXCPLD_LPCI2C_RST_SEL_MASK0x1
+#d
