Re: [patches] [PATCH] [17/58] i386: Add L3 cache support to AMD CPUID4 emulation

2007-07-20 Thread Andreas Herrmann 
I think, Joachim's patch (sent to [EMAIL PROTECTED] on June 14) should
be added as well. I have attached his patch below.


Regards,

Andreas

-- 
Operating | AMD Saxony Limited Liability Company & Co. KG,
  System  | Wilschdorfer Landstr. 101, 01109 Dresden, Germany
 Research | Register Court Dresden: HRA 4896, General Partner authorized
  Center  | to represent: AMD Saxony LLC (Wilmington, Delaware, US)
  (OSRC)  | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy
--

This will allow the size field to be reported for all values instead of a 
handful and also fills the shard_cpu_map with meaning full value.

Signed-off-by: Joachim Deguara <[EMAIL PROTECTED]>
Index: kernel/arch/i386/kernel/cpu/intel_cacheinfo.c
===
--- kernel.orig/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ kernel/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -224,12 +224,7 @@ static void __cpuinit amd_cpuid4(int lea
assoc = l3.assoc;
line_size = l3.line_size;
lines_per_tag = l3.lines_per_tag;
-   switch (l3.size_encoded) {
-   case 4:  size_in_kb = 2 * 1024; break;
-   case 8:  size_in_kb = 4 * 1024; break;
-   case 12: size_in_kb = 6 * 1024; break;
-   default: size_in_kb = 0; break;
-   }
+   size_in_kb = l3.size_encoded * 512;
break;
default:
return;
@@ -238,7 +233,10 @@ static void __cpuinit amd_cpuid4(int lea
eax->split.is_self_initializing = 1;
eax->split.type = types[leaf];
eax->split.level = levels[leaf];
-   eax->split.num_threads_sharing = 0;
+   if (leaf == 3)
+   eax->split.num_threads_sharing = current_cpu_data.x86_max_cores 
- 1;
+   else
+   eax->split.num_threads_sharing = 0;
eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
 
 

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Re: [patches] [PATCH] [17/58] i386: Add L3 cache support to AMD CPUID4 emulation

2007-07-20 Thread Andreas Herrmann 
On Thu, Jul 19, 2007 at 11:55:02AM +0200, Andi Kleen wrote:
> 
> With that an L3 cache is correctly reported in the cache information in /sys
> 
> With fixes from Andreas Herrmann and Dean Gaudet
> 
> Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
> 
> ---
>  arch/i386/kernel/cpu/intel_cacheinfo.c |   74 
> -
>  arch/x86_64/kernel/setup.c |7 ++-
>  2 files changed, 60 insertions(+), 21 deletions(-)

Reporting of L3 cache information should also be enabled in 32bit mode.


Regards,

Andreas
--

Enable reporting of L3 cache info in 32 bit mode for family 0x10.

Signed-off-by: Andreas Herrmann <[EMAIL PROTECTED]>

diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c
index 6f47eee..815a5f0 100644
--- a/arch/i386/kernel/cpu/amd.c
+++ b/arch/i386/kernel/cpu/amd.c
@@ -272,8 +272,12 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
}
 #endif
 
-   if (cpuid_eax(0x8000) >= 0x8006)
-   num_cache_leaves = 3;
+   if (cpuid_eax(0x8000) >= 0x8006) {
+   if ((c->x86 == 0x10) && (cpuid_edx(0x8006) & 0xf000))
+   num_cache_leaves = 4;
+   else
+   num_cache_leaves = 3;
+   }
 
if (amd_apic_timer_broken())
set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability);



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Re: [patches] [PATCH] [17/58] i386: Add L3 cache support to AMD CPUID4 emulation

2007-07-20 Thread Andreas Herrmann 
On Thu, Jul 19, 2007 at 11:55:02AM +0200, Andi Kleen wrote:
 
 With that an L3 cache is correctly reported in the cache information in /sys
 
 With fixes from Andreas Herrmann and Dean Gaudet
 
 Signed-off-by: Andi Kleen [EMAIL PROTECTED]
 
 ---
  arch/i386/kernel/cpu/intel_cacheinfo.c |   74 
 -
  arch/x86_64/kernel/setup.c |7 ++-
  2 files changed, 60 insertions(+), 21 deletions(-)

Reporting of L3 cache information should also be enabled in 32bit mode.


Regards,

Andreas
--

Enable reporting of L3 cache info in 32 bit mode for family 0x10.

Signed-off-by: Andreas Herrmann [EMAIL PROTECTED]

diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c
index 6f47eee..815a5f0 100644
--- a/arch/i386/kernel/cpu/amd.c
+++ b/arch/i386/kernel/cpu/amd.c
@@ -272,8 +272,12 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
}
 #endif
 
-   if (cpuid_eax(0x8000) = 0x8006)
-   num_cache_leaves = 3;
+   if (cpuid_eax(0x8000) = 0x8006) {
+   if ((c-x86 == 0x10)  (cpuid_edx(0x8006)  0xf000))
+   num_cache_leaves = 4;
+   else
+   num_cache_leaves = 3;
+   }
 
if (amd_apic_timer_broken())
set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c-x86_capability);



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Re: [patches] [PATCH] [17/58] i386: Add L3 cache support to AMD CPUID4 emulation

2007-07-20 Thread Andreas Herrmann 
I think, Joachim's patch (sent to [EMAIL PROTECTED] on June 14) should
be added as well. I have attached his patch below.


Regards,

Andreas

-- 
Operating | AMD Saxony Limited Liability Company  Co. KG,
  System  | Wilschdorfer Landstr. 101, 01109 Dresden, Germany
 Research | Register Court Dresden: HRA 4896, General Partner authorized
  Center  | to represent: AMD Saxony LLC (Wilmington, Delaware, US)
  (OSRC)  | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy
--

This will allow the size field to be reported for all values instead of a 
handful and also fills the shard_cpu_map with meaning full value.

Signed-off-by: Joachim Deguara [EMAIL PROTECTED]
Index: kernel/arch/i386/kernel/cpu/intel_cacheinfo.c
===
--- kernel.orig/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ kernel/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -224,12 +224,7 @@ static void __cpuinit amd_cpuid4(int lea
assoc = l3.assoc;
line_size = l3.line_size;
lines_per_tag = l3.lines_per_tag;
-   switch (l3.size_encoded) {
-   case 4:  size_in_kb = 2 * 1024; break;
-   case 8:  size_in_kb = 4 * 1024; break;
-   case 12: size_in_kb = 6 * 1024; break;
-   default: size_in_kb = 0; break;
-   }
+   size_in_kb = l3.size_encoded * 512;
break;
default:
return;
@@ -238,7 +233,10 @@ static void __cpuinit amd_cpuid4(int lea
eax-split.is_self_initializing = 1;
eax-split.type = types[leaf];
eax-split.level = levels[leaf];
-   eax-split.num_threads_sharing = 0;
+   if (leaf == 3)
+   eax-split.num_threads_sharing = current_cpu_data.x86_max_cores 
- 1;
+   else
+   eax-split.num_threads_sharing = 0;
eax-split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
 
 

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