Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Thursday, September 6, 2007 10:50 am Yinghai Lu wrote: > On 9/6/07, Jesse Barnes <[EMAIL PROTECTED]> wrote: > > The problem with doing that is it would mean reserving some address > > space for mmconfig usage. If the BIOS doesn't completely describe > > all the reserved regions via e820 or similar (apparently a common > > problem) we may end up making mmconfig overlap with another > > important area... It's pretty hard not to trust the BIOS here > > without completely replacing big chunks of it. > > for Family 10h, you can use mmio range high beyond than the RAM > range...( just don't conflict with HT reserved range...) Sure, and on some Intel platforms we can configure things similarly. But any such changes will be platform specific. I'm just not sure allocating mmconfig space ourselves is worth the trouble. Besides, most machines made in the last few years can do it, as long as we look at the right BIOS bits (i.e. MCFG not e820) and remember to disable PCI device decode when probing BAR sizes for example. :) Jesse - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 9/6/07, Jesse Barnes <[EMAIL PROTECTED]> wrote: > The problem with doing that is it would mean reserving some address > space for mmconfig usage. If the BIOS doesn't completely describe all > the reserved regions via e820 or similar (apparently a common problem) > we may end up making mmconfig overlap with another important area... > It's pretty hard not to trust the BIOS here without completely > replacing big chunks of it. for Family 10h, you can use mmio range high beyond than the RAM range...( just don't conflict with HT reserved range...) YH - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 9/6/07, H. Peter Anvin <[EMAIL PROTECTED]> wrote: > Well, to a first order of approximations, *all* northbridges have some > sort of hardware registers to set mmconfig. We were talking yesterday > that it might just make more sense to have code for various northbridges > to configure mmconfig directly, just like we do for IRQ routing (we > can't trust the BIOS there, either.) that is good idea. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Thursday, September 6, 2007 2:48 am H. Peter Anvin wrote: > Arne Georg Gleditsch wrote: > > "Yinghai Lu" <[EMAIL PROTECTED]> writes: > >> mmconfig is set in NB ( in new CPU), Do we still need to set > >> mmconfig in SB like mcp55? > > > > I wasn't aware that the family 10h-chips had MSRs for setting the > > mmconfig address space directly in the NB (core?). Please > > disregard my previous comment... > > Well, to a first order of approximations, *all* northbridges have > some sort of hardware registers to set mmconfig. We were talking > yesterday that it might just make more sense to have code for various > northbridges to configure mmconfig directly, just like we do for IRQ > routing (we can't trust the BIOS there, either.) The problem with doing that is it would mean reserving some address space for mmconfig usage. If the BIOS doesn't completely describe all the reserved regions via e820 or similar (apparently a common problem) we may end up making mmconfig overlap with another important area... It's pretty hard not to trust the BIOS here without completely replacing big chunks of it. Jesse - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Wed, 5 Sep 2007 17:00:27 +0200 "Andreas Herrmann" <[EMAIL PROTECTED]> wrote: > On Wed, Sep 05, 2007 at 06:58:58AM +0100, H. Peter Anvin wrote: > > Well, they don't add any functionality, do they? > > They allow CF8/CFC to access ECS in cases where mmcfg is not working. > just for the record; I have absolutely no problem with allowing the new cf8 method (I'm assuming that it's obvious that if mmio is available, that will be used instead for performance reasons). What I was/am concerned/uncomfortable about is keying this off the CPU level rather than a PCI level property; I much rather would see this keyed of, say, the PCI ID of the root bridge, or ideally from some PCI property. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Arne Georg Gleditsch wrote: "Yinghai Lu" <[EMAIL PROTECTED]> writes: mmconfig is set in NB ( in new CPU), Do we still need to set mmconfig in SB like mcp55? I wasn't aware that the family 10h-chips had MSRs for setting the mmconfig address space directly in the NB (core?). Please disregard my previous comment... Well, to a first order of approximations, *all* northbridges have some sort of hardware registers to set mmconfig. We were talking yesterday that it might just make more sense to have code for various northbridges to configure mmconfig directly, just like we do for IRQ routing (we can't trust the BIOS there, either.) -hpa - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
"Yinghai Lu" <[EMAIL PROTECTED]> writes: > mmconfig is set in NB ( in new CPU), Do we still need to set mmconfig > in SB like mcp55? I wasn't aware that the family 10h-chips had MSRs for setting the mmconfig address space directly in the NB (core?). Please disregard my previous comment... -- Arne. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Arne Georg Gleditsch wrote: Yinghai Lu [EMAIL PROTECTED] writes: mmconfig is set in NB ( in new CPU), Do we still need to set mmconfig in SB like mcp55? I wasn't aware that the family 10h-chips had MSRs for setting the mmconfig address space directly in the NB (core?). Please disregard my previous comment... Well, to a first order of approximations, *all* northbridges have some sort of hardware registers to set mmconfig. We were talking yesterday that it might just make more sense to have code for various northbridges to configure mmconfig directly, just like we do for IRQ routing (we can't trust the BIOS there, either.) -hpa - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Wed, 5 Sep 2007 17:00:27 +0200 Andreas Herrmann [EMAIL PROTECTED] wrote: On Wed, Sep 05, 2007 at 06:58:58AM +0100, H. Peter Anvin wrote: Well, they don't add any functionality, do they? They allow CF8/CFC to access ECS in cases where mmcfg is not working. just for the record; I have absolutely no problem with allowing the new cf8 method (I'm assuming that it's obvious that if mmio is available, that will be used instead for performance reasons). What I was/am concerned/uncomfortable about is keying this off the CPU level rather than a PCI level property; I much rather would see this keyed of, say, the PCI ID of the root bridge, or ideally from some PCI property. - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 9/6/07, H. Peter Anvin [EMAIL PROTECTED] wrote: Well, to a first order of approximations, *all* northbridges have some sort of hardware registers to set mmconfig. We were talking yesterday that it might just make more sense to have code for various northbridges to configure mmconfig directly, just like we do for IRQ routing (we can't trust the BIOS there, either.) that is good idea. - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 9/6/07, Jesse Barnes [EMAIL PROTECTED] wrote: The problem with doing that is it would mean reserving some address space for mmconfig usage. If the BIOS doesn't completely describe all the reserved regions via e820 or similar (apparently a common problem) we may end up making mmconfig overlap with another important area... It's pretty hard not to trust the BIOS here without completely replacing big chunks of it. for Family 10h, you can use mmio range high beyond than the RAM range...( just don't conflict with HT reserved range...) YH - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Thursday, September 6, 2007 10:50 am Yinghai Lu wrote: On 9/6/07, Jesse Barnes [EMAIL PROTECTED] wrote: The problem with doing that is it would mean reserving some address space for mmconfig usage. If the BIOS doesn't completely describe all the reserved regions via e820 or similar (apparently a common problem) we may end up making mmconfig overlap with another important area... It's pretty hard not to trust the BIOS here without completely replacing big chunks of it. for Family 10h, you can use mmio range high beyond than the RAM range...( just don't conflict with HT reserved range...) Sure, and on some Intel platforms we can configure things similarly. But any such changes will be platform specific. I'm just not sure allocating mmconfig space ourselves is worth the trouble. Besides, most machines made in the last few years can do it, as long as we look at the right BIOS bits (i.e. MCFG not e820) and remember to disable PCI device decode when probing BAR sizes for example. :) Jesse - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 9/5/07, Andreas Herrmann <[EMAIL PROTECTED]> wrote: > On Wed, Sep 05, 2007 at 01:05:25PM +0200, Arne Georg Gleditsch wrote: > > "H. Peter Anvin" <[EMAIL PROTECTED]> writes: > > > You're missing the point. How will the PCI bus transactions be > > > different when using MMCONFIG versus your extended CF8 version? > > > > Conceivably this is useful if the IO hub does not support MMCONFIG > > accesses. The AMD 8111 does not, as far as I can see. At least I > > have an Opteron system where MMCONFIG is not supported, and I assume > > it's because the 8111 doesn't provide it. I don't know if this is > > going to be a realistic scenario for Barcelona systems. mmconfig is set in NB ( in new CPU), Do we still need to set mmconfig in SB like mcp55? YH - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Wed, Sep 05, 2007 at 01:05:25PM +0200, Arne Georg Gleditsch wrote: > "H. Peter Anvin" <[EMAIL PROTECTED]> writes: > > You're missing the point. How will the PCI bus transactions be > > different when using MMCONFIG versus your extended CF8 version? > > Conceivably this is useful if the IO hub does not support MMCONFIG > accesses. The AMD 8111 does not, as far as I can see. At least I > have an Opteron system where MMCONFIG is not supported, and I assume > it's because the 8111 doesn't provide it. I don't know if this is > going to be a realistic scenario for Barcelona systems. > > -- > Arne. Not sure how many AMD 8111 based systems are out there which are upgradeable to Barcelona. I guess the BIOS won't setup MCFG for systems with 8111/8131 because both lack ECS MMIO Base Address Register. (Because 8111 and 8131 are not Mode2-PCI-X and PCI-express capable.) So if such a board is upgradeable, the way to access extended config space of the northbridge functions is to use CF8/CFC ECS access. Regards, Andreas -- Operating | AMD Saxony Limited Liability Company & Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Wed, Sep 05, 2007 at 06:58:58AM +0100, H. Peter Anvin wrote:
> Well, they don't add any functionality, do they?
They allow CF8/CFC to access ECS in cases where mmcfg is not working.
> As such, I would agree with Andi -- we only
> need one method which can (correctly) access the full configuration space,
Right, we need to be able to "correctly access the full config space".
> since it'll look the same on the bus anyway.
Sure, on the bus we should only see pci configuration requests in both
cases.
To summarize it:
- mmcfg needs support by BIOS ("PCI services in ACPI")
- CF8/CFC ECS access does not have that dependency
- For base configuration space access we already have two methods -
type 1 and mmcfg (type1 as fallback if there is no mmcfg).
- So what's the benefit in not allowing CF8/CFC ECS access ("extended type1")
if the hardware supports it and if mmcfg is not suitable?
One thing that comes out of that fruitless discussion:
For IBS Robert might have to implement CF8/CFC ECS access directly in the IBS
code, or in a new driver for ECS access of NB functions. Just to ensure that
IBS is working if there is no mmcfg. And this is kind of ugly.
Regards,
Andreas
--
Operating | AMD Saxony Limited Liability Company & Co. KG,
System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany
Research | Register Court Dresden: HRA 4896, General Partner authorized
Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US)
(OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy
-
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Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
"H. Peter Anvin" <[EMAIL PROTECTED]> writes: > You're missing the point. How will the PCI bus transactions be > different when using MMCONFIG versus your extended CF8 version? Conceivably this is useful if the IO hub does not support MMCONFIG accesses. The AMD 8111 does not, as far as I can see. At least I have an Opteron system where MMCONFIG is not supported, and I assume it's because the 8111 doesn't provide it. I don't know if this is going to be a realistic scenario for Barcelona systems. -- Arne. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 05.09.07 11:12:00, H. Peter Anvin wrote: > >PCI Devices will not be the same on the bus since PCI read/write > >functions will have different behavior. Without the patches you will > >get an error when accessing ECS with CF8. We need ECS access for > >patches that setups local interrupt vectors. This patches will be > >released soon. > > You're missing the point. How will the PCI bus transactions be > different when using MMCONFIG versus your extended CF8 version? Misunderstood you, with this patch there will be the same behavior, that's the intention. There might be slightly differences in ordering rules for read/write cycles. IO config cycles are serialized while ordering rules for MMIO config cycles may result in unexpected behavior for PCI devices on the bus. -Robert -- Advanced Micro Devices, Inc. Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Robert Richter wrote: On 05.09.07 06:58:58, H. Peter Anvin wrote: But at the moment there is no need for further discussion on this subject because Andi refuses to add support for Barcelona CF8/CFC ECS access. Well, they don't add any functionality, do they? As such, I would agree with Andi -- we only need one method which can (correctly) access the full configuration space, since it'll look the same on the bus anyway. PCI Devices will not be the same on the bus since PCI read/write functions will have different behavior. Without the patches you will get an error when accessing ECS with CF8. We need ECS access for patches that setups local interrupt vectors. This patches will be released soon. You're missing the point. How will the PCI bus transactions be different when using MMCONFIG versus your extended CF8 version? Btw, this patch fixes also config space access with proc/sys fs and lspci. I see this as an added functionality as well. The latter implies the former. Again, how does this differ from MMCONFIG? -hpa - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 05.09.07 06:58:58, H. Peter Anvin wrote: > >But at the moment there is no need for further discussion on this subject > >because Andi refuses to add support for Barcelona CF8/CFC ECS access. > > > > Well, they don't add any functionality, do they? As such, I would agree > with Andi -- we only need one method which can (correctly) access the > full configuration space, since it'll look the same on the bus anyway. PCI Devices will not be the same on the bus since PCI read/write functions will have different behavior. Without the patches you will get an error when accessing ECS with CF8. We need ECS access for patches that setups local interrupt vectors. This patches will be released soon. Btw, this patch fixes also config space access with proc/sys fs and lspci. I see this as an added functionality as well. -Robert -- Advanced Micro Devices, Inc. Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Andreas Herrmann wrote: On Mon, Sep 03, 2007 at 04:33:19AM -0700, Arjan van de Ven wrote: On Mon, 3 Sep 2007 11:17:18 +0200 "Andreas Herrmann" <[EMAIL PROTECTED]> wrote: \> Do you see any other issues besides the naming of the bit? I wonder if we should key this off a PCI ID of the chipset rather than the cpu id... I mean, how sure are you that all via chipsets connected to the barcelona cpu will deal well? In general they should be able to deal with those accesses. They result in extended type 0/1 configuration cycles which are defined already in HT I/O Link Spec 1.10. So if unexpectedly problems arise then it is time to add a pci-quirk. But at the moment there is no need for further discussion on this subject because Andi refuses to add support for Barcelona CF8/CFC ECS access. Well, they don't add any functionality, do they? As such, I would agree with Andi -- we only need one method which can (correctly) access the full configuration space, since it'll look the same on the bus anyway. -hpa - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Andreas Herrmann wrote: On Mon, Sep 03, 2007 at 04:33:19AM -0700, Arjan van de Ven wrote: On Mon, 3 Sep 2007 11:17:18 +0200 Andreas Herrmann [EMAIL PROTECTED] wrote: \ Do you see any other issues besides the naming of the bit? I wonder if we should key this off a PCI ID of the chipset rather than the cpu id... I mean, how sure are you that all via chipsets connected to the barcelona cpu will deal well? In general they should be able to deal with those accesses. They result in extended type 0/1 configuration cycles which are defined already in HT I/O Link Spec 1.10. So if unexpectedly problems arise then it is time to add a pci-quirk. But at the moment there is no need for further discussion on this subject because Andi refuses to add support for Barcelona CF8/CFC ECS access. Well, they don't add any functionality, do they? As such, I would agree with Andi -- we only need one method which can (correctly) access the full configuration space, since it'll look the same on the bus anyway. -hpa - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 05.09.07 06:58:58, H. Peter Anvin wrote: But at the moment there is no need for further discussion on this subject because Andi refuses to add support for Barcelona CF8/CFC ECS access. Well, they don't add any functionality, do they? As such, I would agree with Andi -- we only need one method which can (correctly) access the full configuration space, since it'll look the same on the bus anyway. PCI Devices will not be the same on the bus since PCI read/write functions will have different behavior. Without the patches you will get an error when accessing ECS with CF8. We need ECS access for patches that setups local interrupt vectors. This patches will be released soon. Btw, this patch fixes also config space access with proc/sys fs and lspci. I see this as an added functionality as well. -Robert -- Advanced Micro Devices, Inc. Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Robert Richter wrote: On 05.09.07 06:58:58, H. Peter Anvin wrote: But at the moment there is no need for further discussion on this subject because Andi refuses to add support for Barcelona CF8/CFC ECS access. Well, they don't add any functionality, do they? As such, I would agree with Andi -- we only need one method which can (correctly) access the full configuration space, since it'll look the same on the bus anyway. PCI Devices will not be the same on the bus since PCI read/write functions will have different behavior. Without the patches you will get an error when accessing ECS with CF8. We need ECS access for patches that setups local interrupt vectors. This patches will be released soon. You're missing the point. How will the PCI bus transactions be different when using MMCONFIG versus your extended CF8 version? Btw, this patch fixes also config space access with proc/sys fs and lspci. I see this as an added functionality as well. The latter implies the former. Again, how does this differ from MMCONFIG? -hpa - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 05.09.07 11:12:00, H. Peter Anvin wrote: PCI Devices will not be the same on the bus since PCI read/write functions will have different behavior. Without the patches you will get an error when accessing ECS with CF8. We need ECS access for patches that setups local interrupt vectors. This patches will be released soon. You're missing the point. How will the PCI bus transactions be different when using MMCONFIG versus your extended CF8 version? Misunderstood you, with this patch there will be the same behavior, that's the intention. There might be slightly differences in ordering rules for read/write cycles. IO config cycles are serialized while ordering rules for MMIO config cycles may result in unexpected behavior for PCI devices on the bus. -Robert -- Advanced Micro Devices, Inc. Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
H. Peter Anvin [EMAIL PROTECTED] writes: You're missing the point. How will the PCI bus transactions be different when using MMCONFIG versus your extended CF8 version? Conceivably this is useful if the IO hub does not support MMCONFIG accesses. The AMD 8111 does not, as far as I can see. At least I have an Opteron system where MMCONFIG is not supported, and I assume it's because the 8111 doesn't provide it. I don't know if this is going to be a realistic scenario for Barcelona systems. -- Arne. - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Wed, Sep 05, 2007 at 06:58:58AM +0100, H. Peter Anvin wrote: Well, they don't add any functionality, do they? They allow CF8/CFC to access ECS in cases where mmcfg is not working. As such, I would agree with Andi -- we only need one method which can (correctly) access the full configuration space, Right, we need to be able to correctly access the full config space. since it'll look the same on the bus anyway. Sure, on the bus we should only see pci configuration requests in both cases. To summarize it: - mmcfg needs support by BIOS (PCI services in ACPI) - CF8/CFC ECS access does not have that dependency - For base configuration space access we already have two methods - type 1 and mmcfg (type1 as fallback if there is no mmcfg). - So what's the benefit in not allowing CF8/CFC ECS access (extended type1) if the hardware supports it and if mmcfg is not suitable? One thing that comes out of that fruitless discussion: For IBS Robert might have to implement CF8/CFC ECS access directly in the IBS code, or in a new driver for ECS access of NB functions. Just to ensure that IBS is working if there is no mmcfg. And this is kind of ugly. Regards, Andreas -- Operating | AMD Saxony Limited Liability Company Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Wed, Sep 05, 2007 at 01:05:25PM +0200, Arne Georg Gleditsch wrote: H. Peter Anvin [EMAIL PROTECTED] writes: You're missing the point. How will the PCI bus transactions be different when using MMCONFIG versus your extended CF8 version? Conceivably this is useful if the IO hub does not support MMCONFIG accesses. The AMD 8111 does not, as far as I can see. At least I have an Opteron system where MMCONFIG is not supported, and I assume it's because the 8111 doesn't provide it. I don't know if this is going to be a realistic scenario for Barcelona systems. -- Arne. Not sure how many AMD 8111 based systems are out there which are upgradeable to Barcelona. I guess the BIOS won't setup MCFG for systems with 8111/8131 because both lack ECS MMIO Base Address Register. (Because 8111 and 8131 are not Mode2-PCI-X and PCI-express capable.) So if such a board is upgradeable, the way to access extended config space of the northbridge functions is to use CF8/CFC ECS access. Regards, Andreas -- Operating | AMD Saxony Limited Liability Company Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 9/5/07, Andreas Herrmann [EMAIL PROTECTED] wrote: On Wed, Sep 05, 2007 at 01:05:25PM +0200, Arne Georg Gleditsch wrote: H. Peter Anvin [EMAIL PROTECTED] writes: You're missing the point. How will the PCI bus transactions be different when using MMCONFIG versus your extended CF8 version? Conceivably this is useful if the IO hub does not support MMCONFIG accesses. The AMD 8111 does not, as far as I can see. At least I have an Opteron system where MMCONFIG is not supported, and I assume it's because the 8111 doesn't provide it. I don't know if this is going to be a realistic scenario for Barcelona systems. mmconfig is set in NB ( in new CPU), Do we still need to set mmconfig in SB like mcp55? YH - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
> for setting mmio to accessing pci conf space, need to set sth on MSR. > So the BIOS need to make it right..., otherwise OS need to set that > when booting every cpu...to workaround it to make MMCONFIG working. Yes the BIOS has to get some things right. After all that's the BIOS job. And the BIOS knows much more about the hardware than the generic kernel. x86 Linux is not trying to be a BIOS too. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 9/3/07, Andi Kleen <[EMAIL PROTECTED]> wrote: > On Monday 03 September 2007 13:27, Robert Richter wrote: > > > On 03.09.07 12:15:03, Andi Kleen wrote: > > > > But it is needed for some devices for full functionality. > > > > > > Examples? I can only think of PCI express error reporting, which > > > few drivers implement anyways and isn't really a show stopper > > > if it doesn't work. Besides I would be surprised if it even works > > > on the cheap desktop boards which have MCFG less BIOS. > > > > As you say, there are BIOSs that do not support MMCONFIG. Thus, CF8 > > access is not only a workaround to boot a system. > > We're talking about accessing the extended part of config spaces. I'm not > aware of any case where that is required to boot a system. in the bios for the new cpu, CF8 is used for ext conf space accessing...(for ht and mem init). for setting mmio to accessing pci conf space, need to set sth on MSR. So the BIOS need to make it right..., otherwise OS need to set that when booting every cpu...to workaround it to make MMCONFIG working. YH - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On 9/3/07, Andi Kleen [EMAIL PROTECTED] wrote: On Monday 03 September 2007 13:27, Robert Richter wrote: On 03.09.07 12:15:03, Andi Kleen wrote: But it is needed for some devices for full functionality. Examples? I can only think of PCI express error reporting, which few drivers implement anyways and isn't really a show stopper if it doesn't work. Besides I would be surprised if it even works on the cheap desktop boards which have MCFG less BIOS. As you say, there are BIOSs that do not support MMCONFIG. Thus, CF8 access is not only a workaround to boot a system. We're talking about accessing the extended part of config spaces. I'm not aware of any case where that is required to boot a system. in the bios for the new cpu, CF8 is used for ext conf space accessing...(for ht and mem init). for setting mmio to accessing pci conf space, need to set sth on MSR. So the BIOS need to make it right..., otherwise OS need to set that when booting every cpu...to workaround it to make MMCONFIG working. YH - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
for setting mmio to accessing pci conf space, need to set sth on MSR. So the BIOS need to make it right..., otherwise OS need to set that when booting every cpu...to workaround it to make MMCONFIG working. Yes the BIOS has to get some things right. After all that's the BIOS job. And the BIOS knows much more about the hardware than the generic kernel. x86 Linux is not trying to be a BIOS too. -Andi - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Mon, Sep 03, 2007 at 04:33:19AM -0700, Arjan van de Ven wrote: > On Mon, 3 Sep 2007 11:17:18 +0200 > "Andreas Herrmann" <[EMAIL PROTECTED]> wrote: > \> > > Do you see any other issues besides the naming of the bit? > > I wonder if we should key this off a PCI ID of the chipset rather than > the cpu id... I mean, how sure are you that all via chipsets connected > to the barcelona cpu will deal well? In general they should be able to deal with those accesses. They result in extended type 0/1 configuration cycles which are defined already in HT I/O Link Spec 1.10. So if unexpectedly problems arise then it is time to add a pci-quirk. But at the moment there is no need for further discussion on this subject because Andi refuses to add support for Barcelona CF8/CFC ECS access. Regards, Andreas -- Operating | AMD Saxony Limited Liability Company & Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Monday 03 September 2007 15:48, Robert Richter wrote: > Andi, > > On 03.09.07 14:48:41, Andi Kleen wrote: > > > As said above, I do not see CF8 access as a workaround. I expect my > > > system to work in the same way also if MMCONFIG is not available. > > > > It should boot sure, but exotic stuff not working is not a major issue > > It is not only about booting the system without MMCONFIG, it is also > about using the system There are limits on how many BIOS bug workaround (and all this patch kit is nothing more than a elaborate BIOS bug workaround) we can do. IMHO you're far exceeding the threshold. Better would be to invest that energy to get the BIOSes fixed. > . For this PCI ECS CF8 access is needed. AER and IBS are all totally optional features and the systems will be completely usable without them. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Andi, On 03.09.07 14:48:41, Andi Kleen wrote: > > As said above, I do not see CF8 access as a workaround. I expect my > > system to work in the same way also if MMCONFIG is not available. > > It should boot sure, but exotic stuff not working is not a major issue It is not only about booting the system without MMCONFIG, it is also about using the system. For this PCI ECS CF8 access is needed. So why not adding support for this? Excluding major parts of CPU registers when using CF8 base access only will cause writing code to workaround this. Not very nice to handle. -Robert -- AMD Saxony, Dresden, Germany Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
> And unfortunately this is too often the case. On Barcelona systems? > See for instance Robert Hancock's patch http://lkml.org/lkml/2007/5/30/2 > to enable MMCONFIG access in certain cases where BIOS did not correctly > set up MCFG. Why are people working on such stuff if it is not serious > enough? I don't know why. I'm just not aware of any serious problems that are solved by extended config space access. Originally we had trouble because MCFG was wrong and the systems would not boot. Also there is one class of systems (some x86 Apples) where cf8 doesn't work, but MMCONFIG does. But that's all specific to older systems. > Barcelona just adds another way to access PCI ECS (besides MMCONFIG) and I > can't understand why this shouldn't be supported by Linux. It will be supported when the BIOS gets it right. > Do you have any suggestion how else to add support for PCI ECS access via > IO instructions for Barcelona? My suggestion is to rely on MMCONFIG for this. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Monday 03 September 2007 13:27, Robert Richter wrote: > On 03.09.07 12:15:03, Andi Kleen wrote: > > > But it is needed for some devices for full functionality. > > > > Examples? I can only think of PCI express error reporting, which > > few drivers implement anyways and isn't really a show stopper > > if it doesn't work. Besides I would be surprised if it even works > > on the cheap desktop boards which have MCFG less BIOS. > > As you say, there are BIOSs that do not support MMCONFIG. Thus, CF8 > access is not only a workaround to boot a system. We're talking about accessing the extended part of config spaces. I'm not aware of any case where that is required to boot a system. > Recent (10h) and upcomming CPU families make heavy use of PCI ext cfg > space for certain CPU features. Setup of the extended interupt local > vector table for IBS (used with Perfmon2) is one example. CPU > designers do not take care anymore if a feature is in the base or > extended config space. So access to PCI ECS is essential. I don't think it's a big issue if IBS doesn't work on a few buggy BIOS (which should hopefully become fewer anyways because Vista is out which actually uses MCFG) > > > IMHO it is best to try to use MMCONFIG if it's working and to use > > > a fallback (e.g. CF8 ECS access for family 0x10) if available. > > > > We only put in workarounds if there is a serious problem otherwise (e.g. > > not booting etc.). I just don't see this here. > > As said above, I do not see CF8 access as a workaround. I expect my > system to work in the same way also if MMCONFIG is not available. It should boot sure, but exotic stuff not working is not a major issue -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Mon, 3 Sep 2007 11:17:18 +0200 "Andreas Herrmann" <[EMAIL PROTECTED]> wrote: \> > Do you see any other issues besides the naming of the bit? I wonder if we should key this off a PCI ID of the chipset rather than the cpu id... I mean, how sure are you that all via chipsets connected to the barcelona cpu will deal well? - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Mon, Sep 03, 2007 at 12:15:03PM +0200, Andi Kleen wrote: > > > But it is needed for some devices for full functionality. > > Examples? I can only think of PCI express error reporting, which > few drivers implement anyways and isn't really a show stopper > if it doesn't work. Besides I would be surprised if it even works > on the cheap desktop boards which have MCFG less BIOS. Sure, AER is one example. I don't see why all other stuff in ECS is not worth reading or writing. And I am not sure whether all server boards set up MCFG in the correct way. > > E.g. for perfmon (family 0x10/extended inerrupts) extended config space > > access is a prerequisite. > > How so? E.g. access to the IBS control register needs ECS access on Barcelona. I guess we have to wait until Robert sends his patches which contain all details. > > > > IMHO it is best to try to use MMCONFIG if it's working and to use > > a fallback (e.g. CF8 ECS access for family 0x10) if available. > > We only put in workarounds if there is a serious problem otherwise (e.g. not > booting etc.). I just don't see this here. The serious problem is you can't access PCI ECS if the BIOS does not take care to (correctly) set up MCFG. And unfortunately this is too often the case. See for instance Robert Hancock's patch http://lkml.org/lkml/2007/5/30/2 to enable MMCONFIG access in certain cases where BIOS did not correctly set up MCFG. Why are people working on such stuff if it is not serious enough? Barcelona just adds another way to access PCI ECS (besides MMCONFIG) and I can't understand why this shouldn't be supported by Linux. Do you have any suggestion how else to add support for PCI ECS access via IO instructions for Barcelona? Regards, Andreas -- Operating | AMD Saxony Limited Liability Company & Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Andi, On 03.09.07 12:15:03, Andi Kleen wrote: > > But it is needed for some devices for full functionality. > > Examples? I can only think of PCI express error reporting, which > few drivers implement anyways and isn't really a show stopper > if it doesn't work. Besides I would be surprised if it even works > on the cheap desktop boards which have MCFG less BIOS. As you say, there are BIOSs that do not support MMCONFIG. Thus, CF8 access is not only a workaround to boot a system. There are systems that really use CF8 access. Also, MMCONFIG depends on many conditions that must match. Cfg space must be mapped, the memory must be E820 reserved, MCFG table must be set, access to MMCONFIG must be enabled for the device. Many things that may fail and can partly not be fixed by the OS. > > E.g. for perfmon (family 0x10/extended inerrupts) extended config space > > access is a prerequisite. > > How so? Recent (10h) and upcomming CPU families make heavy use of PCI ext cfg space for certain CPU features. Setup of the extended interupt local vector table for IBS (used with Perfmon2) is one example. CPU designers do not take care anymore if a feature is in the base or extended config space. So access to PCI ECS is essential. > > IMHO it is best to try to use MMCONFIG if it's working and to use > > a fallback (e.g. CF8 ECS access for family 0x10) if available. > > We only put in workarounds if there is a serious problem otherwise (e.g. not > booting etc.). I just don't see this here. As said above, I do not see CF8 access as a workaround. I expect my system to work in the same way also if MMCONFIG is not available. -Robert -- AMD Saxony, Dresden, Germany Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
> But it is needed for some devices for full functionality. Examples? I can only think of PCI express error reporting, which few drivers implement anyways and isn't really a show stopper if it doesn't work. Besides I would be surprised if it even works on the cheap desktop boards which have MCFG less BIOS. > E.g. for perfmon (family 0x10/extended inerrupts) extended config space > access is a prerequisite. How so? > > IMHO it is best to try to use MMCONFIG if it's working and to use > a fallback (e.g. CF8 ECS access for family 0x10) if available. We only put in workarounds if there is a serious problem otherwise (e.g. not booting etc.). I just don't see this here. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Mon, Sep 03, 2007 at 01:31:57AM -0700, Arjan van de Ven wrote: > On Mon, 03 Sep 2007 10:17:39 +0200 > "Robert Richter" <[EMAIL PROTECTED]> wrote: > > > This patch implements PCI extended configuration space access for > > AMD's Barcelona CPUs. It extends the method using CF8/CFC IO > > addresses. An x86 capability bit has been introduced that is set for > > CPUs supporting PCI extended config space accesses. > > > > > No offence but this feels a bit wrong to me. > > PCI is sort of more a chipset property than a cpu property (I realize > that this boundary is changing of course). > > I'd like to ask you to at least rename some of the feature bits to > indicate that the extended config space is for the IO access method; > after all Linux already supports the MMIO method for accessing extended > config space since a really long time; not marking the feature bit to > indicate it's the IO method is going to be extremely confusing and > cause bugs I bet. Hmm, yes the naming of the CPU capability bit seems wrong. Guess, Robert will fix it. > (we probably need a global function that drivers can use to find out of > extended config space is accessible; however that for sure isn't a CPU > capability bit. IMHO this is already available. Just check pci_dev->cfg_size which is 256 if PCI ECS access is not possible (see pci_cfg_space_size()). > However the current naming etc sort of makes me fear > drivers will abuse this thing while thinking it's the right API) Do you see any other issues besides the naming of the bit? Regards, Andreas -- Operating | AMD Saxony Limited Liability Company & Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Sat, Sep 01, 2007 at 12:11:52PM +0200, Andi Kleen wrote: > On Thursday 30 August 2007 19:43:14 Robert Richter wrote: > > This patch implements PCI extended configuration space access for > > AMD's Barcelona CPUs. It extends the method using CF8/CFC IO > > addresses. An x86 capability bit has been introduced that is set for > > CPUs supporting PCI extended config space accesses. > > We shouldn't need this because extended config space should work > here and Linux should use it > (especially after we added the ugly Barcelona workaround into that code) This patch is needed for all buggy BIOSes that don't correctly set up MCFG. > The only exception would be if the user disables MMCONFIG in CONFIG, but > that's > their own fault then. No, as you stated yourself there are two exceptions. And the more serious one is the BIOS issue. > Ok there might be buggy BIOS around with no or no usable MCFG table, but since > extended config space is not really a critical feature that's not a big issue. Not sure why you assume extended config space (ECS) is not critical. Ok, for a lot of stuff it does not matter. But it is needed for some devices for full functionality. E.g. for perfmon (family 0x10/extended inerrupts) extended config space access is a prerequisite. > So I don't think we want this special case code at all and should > just rely on MMCONFIG. Rely on something unreliable (due to buggy/incomplete BIOS)? I don't think we should do this. IMHO it is best to try to use MMCONFIG if it's working and to use a fallback (e.g. CF8 ECS access for family 0x10) if available. Regards, Andreas -- Operating | AMD Saxony Limited Liability Company & Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Sat, Sep 01, 2007 at 12:11:52PM +0200, Andi Kleen wrote: On Thursday 30 August 2007 19:43:14 Robert Richter wrote: This patch implements PCI extended configuration space access for AMD's Barcelona CPUs. It extends the method using CF8/CFC IO addresses. An x86 capability bit has been introduced that is set for CPUs supporting PCI extended config space accesses. We shouldn't need this because extended config space should work here and Linux should use it (especially after we added the ugly Barcelona workaround into that code) This patch is needed for all buggy BIOSes that don't correctly set up MCFG. The only exception would be if the user disables MMCONFIG in CONFIG, but that's their own fault then. No, as you stated yourself there are two exceptions. And the more serious one is the BIOS issue. Ok there might be buggy BIOS around with no or no usable MCFG table, but since extended config space is not really a critical feature that's not a big issue. Not sure why you assume extended config space (ECS) is not critical. Ok, for a lot of stuff it does not matter. But it is needed for some devices for full functionality. E.g. for perfmon (family 0x10/extended inerrupts) extended config space access is a prerequisite. So I don't think we want this special case code at all and should just rely on MMCONFIG. Rely on something unreliable (due to buggy/incomplete BIOS)? I don't think we should do this. IMHO it is best to try to use MMCONFIG if it's working and to use a fallback (e.g. CF8 ECS access for family 0x10) if available. Regards, Andreas -- Operating | AMD Saxony Limited Liability Company Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Mon, Sep 03, 2007 at 01:31:57AM -0700, Arjan van de Ven wrote: On Mon, 03 Sep 2007 10:17:39 +0200 Robert Richter [EMAIL PROTECTED] wrote: This patch implements PCI extended configuration space access for AMD's Barcelona CPUs. It extends the method using CF8/CFC IO addresses. An x86 capability bit has been introduced that is set for CPUs supporting PCI extended config space accesses. No offence but this feels a bit wrong to me. PCI is sort of more a chipset property than a cpu property (I realize that this boundary is changing of course). I'd like to ask you to at least rename some of the feature bits to indicate that the extended config space is for the IO access method; after all Linux already supports the MMIO method for accessing extended config space since a really long time; not marking the feature bit to indicate it's the IO method is going to be extremely confusing and cause bugs I bet. Hmm, yes the naming of the CPU capability bit seems wrong. Guess, Robert will fix it. (we probably need a global function that drivers can use to find out of extended config space is accessible; however that for sure isn't a CPU capability bit. IMHO this is already available. Just check pci_dev-cfg_size which is 256 if PCI ECS access is not possible (see pci_cfg_space_size()). However the current naming etc sort of makes me fear drivers will abuse this thing while thinking it's the right API) Do you see any other issues besides the naming of the bit? Regards, Andreas -- Operating | AMD Saxony Limited Liability Company Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
But it is needed for some devices for full functionality. Examples? I can only think of PCI express error reporting, which few drivers implement anyways and isn't really a show stopper if it doesn't work. Besides I would be surprised if it even works on the cheap desktop boards which have MCFG less BIOS. E.g. for perfmon (family 0x10/extended inerrupts) extended config space access is a prerequisite. How so? IMHO it is best to try to use MMCONFIG if it's working and to use a fallback (e.g. CF8 ECS access for family 0x10) if available. We only put in workarounds if there is a serious problem otherwise (e.g. not booting etc.). I just don't see this here. -Andi - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Andi, On 03.09.07 12:15:03, Andi Kleen wrote: But it is needed for some devices for full functionality. Examples? I can only think of PCI express error reporting, which few drivers implement anyways and isn't really a show stopper if it doesn't work. Besides I would be surprised if it even works on the cheap desktop boards which have MCFG less BIOS. As you say, there are BIOSs that do not support MMCONFIG. Thus, CF8 access is not only a workaround to boot a system. There are systems that really use CF8 access. Also, MMCONFIG depends on many conditions that must match. Cfg space must be mapped, the memory must be E820 reserved, MCFG table must be set, access to MMCONFIG must be enabled for the device. Many things that may fail and can partly not be fixed by the OS. E.g. for perfmon (family 0x10/extended inerrupts) extended config space access is a prerequisite. How so? Recent (10h) and upcomming CPU families make heavy use of PCI ext cfg space for certain CPU features. Setup of the extended interupt local vector table for IBS (used with Perfmon2) is one example. CPU designers do not take care anymore if a feature is in the base or extended config space. So access to PCI ECS is essential. IMHO it is best to try to use MMCONFIG if it's working and to use a fallback (e.g. CF8 ECS access for family 0x10) if available. We only put in workarounds if there is a serious problem otherwise (e.g. not booting etc.). I just don't see this here. As said above, I do not see CF8 access as a workaround. I expect my system to work in the same way also if MMCONFIG is not available. -Robert -- AMD Saxony, Dresden, Germany Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Mon, Sep 03, 2007 at 12:15:03PM +0200, Andi Kleen wrote: But it is needed for some devices for full functionality. Examples? I can only think of PCI express error reporting, which few drivers implement anyways and isn't really a show stopper if it doesn't work. Besides I would be surprised if it even works on the cheap desktop boards which have MCFG less BIOS. Sure, AER is one example. I don't see why all other stuff in ECS is not worth reading or writing. And I am not sure whether all server boards set up MCFG in the correct way. E.g. for perfmon (family 0x10/extended inerrupts) extended config space access is a prerequisite. How so? E.g. access to the IBS control register needs ECS access on Barcelona. I guess we have to wait until Robert sends his patches which contain all details. IMHO it is best to try to use MMCONFIG if it's working and to use a fallback (e.g. CF8 ECS access for family 0x10) if available. We only put in workarounds if there is a serious problem otherwise (e.g. not booting etc.). I just don't see this here. The serious problem is you can't access PCI ECS if the BIOS does not take care to (correctly) set up MCFG. And unfortunately this is too often the case. See for instance Robert Hancock's patch http://lkml.org/lkml/2007/5/30/2 to enable MMCONFIG access in certain cases where BIOS did not correctly set up MCFG. Why are people working on such stuff if it is not serious enough? Barcelona just adds another way to access PCI ECS (besides MMCONFIG) and I can't understand why this shouldn't be supported by Linux. Do you have any suggestion how else to add support for PCI ECS access via IO instructions for Barcelona? Regards, Andreas -- Operating | AMD Saxony Limited Liability Company Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Mon, 3 Sep 2007 11:17:18 +0200 Andreas Herrmann [EMAIL PROTECTED] wrote: \ Do you see any other issues besides the naming of the bit? I wonder if we should key this off a PCI ID of the chipset rather than the cpu id... I mean, how sure are you that all via chipsets connected to the barcelona cpu will deal well? - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
And unfortunately this is too often the case. On Barcelona systems? See for instance Robert Hancock's patch http://lkml.org/lkml/2007/5/30/2 to enable MMCONFIG access in certain cases where BIOS did not correctly set up MCFG. Why are people working on such stuff if it is not serious enough? I don't know why. I'm just not aware of any serious problems that are solved by extended config space access. Originally we had trouble because MCFG was wrong and the systems would not boot. Also there is one class of systems (some x86 Apples) where cf8 doesn't work, but MMCONFIG does. But that's all specific to older systems. Barcelona just adds another way to access PCI ECS (besides MMCONFIG) and I can't understand why this shouldn't be supported by Linux. It will be supported when the BIOS gets it right. Do you have any suggestion how else to add support for PCI ECS access via IO instructions for Barcelona? My suggestion is to rely on MMCONFIG for this. -Andi - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Monday 03 September 2007 13:27, Robert Richter wrote: On 03.09.07 12:15:03, Andi Kleen wrote: But it is needed for some devices for full functionality. Examples? I can only think of PCI express error reporting, which few drivers implement anyways and isn't really a show stopper if it doesn't work. Besides I would be surprised if it even works on the cheap desktop boards which have MCFG less BIOS. As you say, there are BIOSs that do not support MMCONFIG. Thus, CF8 access is not only a workaround to boot a system. We're talking about accessing the extended part of config spaces. I'm not aware of any case where that is required to boot a system. Recent (10h) and upcomming CPU families make heavy use of PCI ext cfg space for certain CPU features. Setup of the extended interupt local vector table for IBS (used with Perfmon2) is one example. CPU designers do not take care anymore if a feature is in the base or extended config space. So access to PCI ECS is essential. I don't think it's a big issue if IBS doesn't work on a few buggy BIOS (which should hopefully become fewer anyways because Vista is out which actually uses MCFG) IMHO it is best to try to use MMCONFIG if it's working and to use a fallback (e.g. CF8 ECS access for family 0x10) if available. We only put in workarounds if there is a serious problem otherwise (e.g. not booting etc.). I just don't see this here. As said above, I do not see CF8 access as a workaround. I expect my system to work in the same way also if MMCONFIG is not available. It should boot sure, but exotic stuff not working is not a major issue -Andi - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
Andi, On 03.09.07 14:48:41, Andi Kleen wrote: As said above, I do not see CF8 access as a workaround. I expect my system to work in the same way also if MMCONFIG is not available. It should boot sure, but exotic stuff not working is not a major issue It is not only about booting the system without MMCONFIG, it is also about using the system. For this PCI ECS CF8 access is needed. So why not adding support for this? Excluding major parts of CPU registers when using CF8 base access only will cause writing code to workaround this. Not very nice to handle. -Robert -- AMD Saxony, Dresden, Germany Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Monday 03 September 2007 15:48, Robert Richter wrote: Andi, On 03.09.07 14:48:41, Andi Kleen wrote: As said above, I do not see CF8 access as a workaround. I expect my system to work in the same way also if MMCONFIG is not available. It should boot sure, but exotic stuff not working is not a major issue It is not only about booting the system without MMCONFIG, it is also about using the system There are limits on how many BIOS bug workaround (and all this patch kit is nothing more than a elaborate BIOS bug workaround) we can do. IMHO you're far exceeding the threshold. Better would be to invest that energy to get the BIOSes fixed. . For this PCI ECS CF8 access is needed. AER and IBS are all totally optional features and the systems will be completely usable without them. -Andi - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona
On Mon, Sep 03, 2007 at 04:33:19AM -0700, Arjan van de Ven wrote: On Mon, 3 Sep 2007 11:17:18 +0200 Andreas Herrmann [EMAIL PROTECTED] wrote: \ Do you see any other issues besides the naming of the bit? I wonder if we should key this off a PCI ID of the chipset rather than the cpu id... I mean, how sure are you that all via chipsets connected to the barcelona cpu will deal well? In general they should be able to deal with those accesses. They result in extended type 0/1 configuration cycles which are defined already in HT I/O Link Spec 1.10. So if unexpectedly problems arise then it is time to add a pci-quirk. But at the moment there is no need for further discussion on this subject because Andi refuses to add support for Barcelona CF8/CFC ECS access. Regards, Andreas -- Operating | AMD Saxony Limited Liability Company Co. KG, System | Wilschdorfer Landstr. 101, 01109 Dresden, Germany Research | Register Court Dresden: HRA 4896, General Partner authorized Center | to represent: AMD Saxony LLC (Wilmington, Delaware, US) (OSRC) | General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy - To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
