[tip: objtool/core] objtool,x86: Support %riz encodings
The following commit has been merged into the objtool/core branch of tip:
Commit-ID: 78df6245c3c82484200b9f8e306dc86fb19e9c02
Gitweb:
https://git.kernel.org/tip/78df6245c3c82484200b9f8e306dc86fb19e9c02
Author:Peter Zijlstra
AuthorDate:Wed, 10 Feb 2021 11:47:35 +01:00
Committer: Ingo Molnar
CommitterDate: Sat, 06 Mar 2021 12:44:23 +01:00
objtool,x86: Support %riz encodings
When there's a SIB byte, the register otherwise denoted by r/m will
then be denoted by SIB.base REX.b will now extend this. SIB.index == SP
is magic and notes an index value zero.
This means that there's a bunch of alternative (longer) encodings for
the same thing. Eg. 'ModRM.mod != 3, ModRM.r/m = AX' can be encoded as
'ModRM.mod != 3, ModRM.r/m = SP, SIB.base = AX, SIB.index = SP' which is
actually 4
different encodings because the value of SIB.scale is irrelevant,
giving rise to 5 different but equal encodings.
Support these encodings and clean up the SIB handling in general.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Acked-by: Josh Poimboeuf
Tested-by: Nick Desaulniers
Link: https://lkml.kernel.org/r/20210211173627.472967...@infradead.org
---
tools/objtool/arch/x86/decode.c | 67 ++--
1 file changed, 48 insertions(+), 19 deletions(-)
diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c
index 5ce7dc4..78ae5be 100644
--- a/tools/objtool/arch/x86/decode.c
+++ b/tools/objtool/arch/x86/decode.c
@@ -72,6 +72,25 @@ unsigned long arch_jump_destination(struct instruction *insn)
return -1; \
else for (list_add_tail(>list, ops_list); op; op = NULL)
+/*
+ * Helpers to decode ModRM/SIB:
+ *
+ * r/m| AX CX DX BX | SP | BP | SI DI |
+ *| R8 R9 R10 R11 | R12 | R13 | R14 R15 |
+ * Mod++-+-+-+
+ * 00 |[r/m] |[SIB]|[IP+]| [r/m] |
+ * 01 | [r/m + d8]|[S+d]| [r/m + d8] |
+ * 10 | [r/m + d32] |[S+D]| [r/m + d32] |
+ * 11 | r/ m |
+ *
+ */
+#define is_RIP() ((modrm_rm & 7) == CFI_BP && modrm_mod == 0)
+#define have_SIB() ((modrm_rm & 7) == CFI_SP && modrm_mod != 3)
+
+#define rm_is(reg) (have_SIB() ? \
+ sib_base == (reg) && sib_index == CFI_SP : \
+ modrm_rm == (reg))
+
int arch_decode_instruction(const struct elf *elf, const struct section *sec,
unsigned long offset, unsigned int maxlen,
unsigned int *len, enum insn_type *type,
@@ -83,7 +102,7 @@ int arch_decode_instruction(const struct elf *elf, const
struct section *sec,
unsigned char op1, op2,
rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0,
modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,
- sib = 0 /* , sib_scale = 0, sib_index = 0, sib_base = 0
*/;
+ sib = 0, /* sib_scale = 0, */ sib_index = 0, sib_base = 0;
struct stack_op *op = NULL;
struct symbol *sym;
@@ -125,11 +144,9 @@ int arch_decode_instruction(const struct elf *elf, const
struct section *sec,
if (insn.sib.nbytes) {
sib = insn.sib.bytes[0];
- /*
- sib_scale = X86_SIB_SCALE(sib);
+ /* sib_scale = X86_SIB_SCALE(sib); */
sib_index = X86_SIB_INDEX(sib) + 8*rex_x;
sib_base = X86_SIB_BASE(sib) + 8*rex_b;
-*/
}
switch (op1) {
@@ -218,7 +235,10 @@ int arch_decode_instruction(const struct elf *elf, const
struct section *sec,
break;
case 0x89:
- if (rex_w && modrm_reg == CFI_SP) {
+ if (!rex_w)
+ break;
+
+ if (modrm_reg == CFI_SP) {
if (modrm_mod == 3) {
/* mov %rsp, reg */
@@ -231,14 +251,17 @@ int arch_decode_instruction(const struct elf *elf, const
struct section *sec,
break;
} else {
- /* skip nontrivial SIB */
- if ((modrm_rm & 7) == 4 && !(sib == 0x24 &&
rex_b == rex_x))
- break;
-
/* skip RIP relative displacement */
- if ((modrm_rm & 7) == 5 && modrm_mod == 0)
+ if (is_RIP())
break;
+ /* skip nontrivial SIB */
+ if (have_SIB()) {
+ modrm_rm = sib_base;
+ if (sib_index != CFI_SP)
+ break;
+ }
+
/* mov %rsp, disp(%reg) */
ADD_OP(op) {
[tip: objtool/core] objtool,x86: Support %riz encodings
The following commit has been merged into the objtool/core branch of tip:
Commit-ID: 0a8bef63e5bf4496251f7bac4ddadb5f5f489932
Gitweb:
https://git.kernel.org/tip/0a8bef63e5bf4496251f7bac4ddadb5f5f489932
Author:Peter Zijlstra
AuthorDate:Wed, 10 Feb 2021 11:47:35 +01:00
Committer: Peter Zijlstra
CommitterDate: Wed, 03 Mar 2021 09:38:30 +01:00
objtool,x86: Support %riz encodings
When there's a SIB byte, the register otherwise denoted by r/m will
then be denoted by SIB.base REX.b will now extend this. SIB.index == SP
is magic and notes an index value zero.
This means that there's a bunch of alternative (longer) encodings for
the same thing. Eg. 'ModRM.mod != 3, ModRM.r/m = AX' can be encoded as
'ModRM.mod != 3, ModRM.r/m = SP, SIB.base = AX, SIB.index = SP' which is
actually 4
different encodings because the value of SIB.scale is irrelevant,
giving rise to 5 different but equal encodings.
Support these encodings and clean up the SIB handling in general.
Signed-off-by: Peter Zijlstra (Intel)
Acked-by: Josh Poimboeuf
Tested-by: Nick Desaulniers
Link: https://lkml.kernel.org/r/20210211173627.472967...@infradead.org
---
tools/objtool/arch/x86/decode.c | 67 ++--
1 file changed, 48 insertions(+), 19 deletions(-)
diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c
index 5ce7dc4..78ae5be 100644
--- a/tools/objtool/arch/x86/decode.c
+++ b/tools/objtool/arch/x86/decode.c
@@ -72,6 +72,25 @@ unsigned long arch_jump_destination(struct instruction *insn)
return -1; \
else for (list_add_tail(>list, ops_list); op; op = NULL)
+/*
+ * Helpers to decode ModRM/SIB:
+ *
+ * r/m| AX CX DX BX | SP | BP | SI DI |
+ *| R8 R9 R10 R11 | R12 | R13 | R14 R15 |
+ * Mod++-+-+-+
+ * 00 |[r/m] |[SIB]|[IP+]| [r/m] |
+ * 01 | [r/m + d8]|[S+d]| [r/m + d8] |
+ * 10 | [r/m + d32] |[S+D]| [r/m + d32] |
+ * 11 | r/ m |
+ *
+ */
+#define is_RIP() ((modrm_rm & 7) == CFI_BP && modrm_mod == 0)
+#define have_SIB() ((modrm_rm & 7) == CFI_SP && modrm_mod != 3)
+
+#define rm_is(reg) (have_SIB() ? \
+ sib_base == (reg) && sib_index == CFI_SP : \
+ modrm_rm == (reg))
+
int arch_decode_instruction(const struct elf *elf, const struct section *sec,
unsigned long offset, unsigned int maxlen,
unsigned int *len, enum insn_type *type,
@@ -83,7 +102,7 @@ int arch_decode_instruction(const struct elf *elf, const
struct section *sec,
unsigned char op1, op2,
rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0,
modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,
- sib = 0 /* , sib_scale = 0, sib_index = 0, sib_base = 0
*/;
+ sib = 0, /* sib_scale = 0, */ sib_index = 0, sib_base = 0;
struct stack_op *op = NULL;
struct symbol *sym;
@@ -125,11 +144,9 @@ int arch_decode_instruction(const struct elf *elf, const
struct section *sec,
if (insn.sib.nbytes) {
sib = insn.sib.bytes[0];
- /*
- sib_scale = X86_SIB_SCALE(sib);
+ /* sib_scale = X86_SIB_SCALE(sib); */
sib_index = X86_SIB_INDEX(sib) + 8*rex_x;
sib_base = X86_SIB_BASE(sib) + 8*rex_b;
-*/
}
switch (op1) {
@@ -218,7 +235,10 @@ int arch_decode_instruction(const struct elf *elf, const
struct section *sec,
break;
case 0x89:
- if (rex_w && modrm_reg == CFI_SP) {
+ if (!rex_w)
+ break;
+
+ if (modrm_reg == CFI_SP) {
if (modrm_mod == 3) {
/* mov %rsp, reg */
@@ -231,14 +251,17 @@ int arch_decode_instruction(const struct elf *elf, const
struct section *sec,
break;
} else {
- /* skip nontrivial SIB */
- if ((modrm_rm & 7) == 4 && !(sib == 0x24 &&
rex_b == rex_x))
- break;
-
/* skip RIP relative displacement */
- if ((modrm_rm & 7) == 5 && modrm_mod == 0)
+ if (is_RIP())
break;
+ /* skip nontrivial SIB */
+ if (have_SIB()) {
+ modrm_rm = sib_base;
+ if (sib_index != CFI_SP)
+ break;
+ }
+
/* mov %rsp, disp(%reg) */
ADD_OP(op) {
