[tip:perf/x86] x86: Add support for Intel Cache QoS Monitoring ( CQM) detection
Commit-ID: cbc82b17263877ea5d21e84c58ce03f0292458a1
Gitweb: http://git.kernel.org/tip/cbc82b17263877ea5d21e84c58ce03f0292458a1
Author: Peter P Waskiewicz Jr
AuthorDate: Fri, 23 Jan 2015 18:45:43 +
Committer: Ingo Molnar
CommitDate: Wed, 25 Feb 2015 13:53:31 +0100
x86: Add support for Intel Cache QoS Monitoring (CQM) detection
This patch adds support for the new Cache QoS Monitoring (CQM)
feature found in future Intel Xeon processors. It includes the
new values to track CQM resources to the cpuinfo_x86 structure,
plus the CPUID detection routines for CQM.
CQM allows a process, or set of processes, to be tracked by the CPU
to determine the cache usage of that task group. Using this data
from the CPU, software can be written to extract this data and
report cache usage and occupancy for a particular process, or
group of processes.
More information about Cache QoS Monitoring can be found in the
Intel (R) x86 Architecture Software Developer Manual, section 17.14.
Signed-off-by: Peter P Waskiewicz Jr
Signed-off-by: Matt Fleming
Signed-off-by: Peter Zijlstra (Intel)
Cc: Andy Lutomirski
Cc: Arnaldo Carvalho de Melo
Cc: Borislav Petkov
Cc: Chris Webb
Cc: Dave Hansen
Cc: Fenghua Yu
Cc: H. Peter Anvin
Cc: Igor Mammedov
Cc: Jacob Shin
Cc: Jan Beulich
Cc: Jiri Olsa
Cc: Kanaka Juvva
Cc: Linus Torvalds
Cc: Steven Honeyman
Cc: Steven Rostedt
Cc: Vikas Shivappa
Link:
http://lkml.kernel.org/r/1422038748-21397-5-git-send-email-m...@codeblueprint.co.uk
Signed-off-by: Ingo Molnar
---
arch/x86/include/asm/cpufeature.h | 9 -
arch/x86/include/asm/processor.h | 3 +++
arch/x86/kernel/cpu/common.c | 39 +++
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeature.h
b/arch/x86/include/asm/cpufeature.h
index 90a5485..361922d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
#include
#endif
-#define NCAPINTS 11 /* N 32-bit words worth of info */
+#define NCAPINTS 13 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -226,6 +226,7 @@
#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID( 9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM( 9*32+11) /* Restricted Transactional
Memory */
+#define X86_FEATURE_CQM( 9*32+12) /* Cache QoS Monitoring */
#define X86_FEATURE_MPX( 9*32+14) /* Memory Protection
Extension */
#define X86_FEATURE_AVX512F( 9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
@@ -242,6 +243,12 @@
#define X86_FEATURE_XGETBV1(10*32+ 2) /* XGETBV with ECX = 1 */
#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
+/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x000F:0 (edx), word 11 */
+#define X86_FEATURE_CQM_LLC(11*32+ 1) /* LLC QoS if 1 */
+
+/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x000F:1 (edx), word 12 */
+#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1
*/
+
/*
* BUG word(s)
*/
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index ec1c935..a12d50e 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -109,6 +109,9 @@ struct cpuinfo_x86 {
/* in KB - valid for CPUS which support this call: */
int x86_cache_size;
int x86_cache_alignment;/* In bytes */
+ /* Cache QoS architectural values: */
+ int x86_cache_max_rmid; /* max index */
+ int x86_cache_occ_scale;/* scale to bytes */
int x86_power;
unsigned long loops_per_jiffy;
/* cpuid returned max cores value: */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 07f2fc3..9fa00b2 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -645,6 +645,30 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_capability[10] = eax;
}
+ /* Additional Intel-defined flags: level 0x000F */
+ if (c->cpuid_level >= 0x000F) {
+ u32 eax, ebx, ecx, edx;
+
+ /* QoS sub-leaf, EAX=0Fh, ECX=0 */
+ cpuid_count(0x000F, 0, , , , );
+ c->x86_capability[11] = edx;
+ if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
+ /* will be overridden if occupancy monitoring exists */
+ c->x86_cache_max_rmid = ebx;
+
+ /* QoS sub-leaf, EAX=0Fh, ECX=1 */
+ cpuid_count(0x000F, 1, , , , );
+ c->x86_capability[12] = edx;
+ if (cpu_has(c,
[tip:perf/x86] x86: Add support for Intel Cache QoS Monitoring ( CQM) detection
Commit-ID: cbc82b17263877ea5d21e84c58ce03f0292458a1
Gitweb: http://git.kernel.org/tip/cbc82b17263877ea5d21e84c58ce03f0292458a1
Author: Peter P Waskiewicz Jr peter.p.waskiewicz...@intel.com
AuthorDate: Fri, 23 Jan 2015 18:45:43 +
Committer: Ingo Molnar mi...@kernel.org
CommitDate: Wed, 25 Feb 2015 13:53:31 +0100
x86: Add support for Intel Cache QoS Monitoring (CQM) detection
This patch adds support for the new Cache QoS Monitoring (CQM)
feature found in future Intel Xeon processors. It includes the
new values to track CQM resources to the cpuinfo_x86 structure,
plus the CPUID detection routines for CQM.
CQM allows a process, or set of processes, to be tracked by the CPU
to determine the cache usage of that task group. Using this data
from the CPU, software can be written to extract this data and
report cache usage and occupancy for a particular process, or
group of processes.
More information about Cache QoS Monitoring can be found in the
Intel (R) x86 Architecture Software Developer Manual, section 17.14.
Signed-off-by: Peter P Waskiewicz Jr peter.p.waskiewicz...@intel.com
Signed-off-by: Matt Fleming matt.flem...@intel.com
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
Cc: Andy Lutomirski l...@amacapital.net
Cc: Arnaldo Carvalho de Melo a...@kernel.org
Cc: Borislav Petkov b...@suse.de
Cc: Chris Webb ch...@arachsys.com
Cc: Dave Hansen dave.han...@linux.intel.com
Cc: Fenghua Yu fenghua...@intel.com
Cc: H. Peter Anvin h...@zytor.com
Cc: Igor Mammedov imamm...@redhat.com
Cc: Jacob Shin jacob.w.s...@gmail.com
Cc: Jan Beulich jbeul...@suse.com
Cc: Jiri Olsa jo...@redhat.com
Cc: Kanaka Juvva kanaka.d.ju...@intel.com
Cc: Linus Torvalds torva...@linux-foundation.org
Cc: Steven Honeyman stevenhoney...@gmail.com
Cc: Steven Rostedt srost...@redhat.com
Cc: Vikas Shivappa vikas.shiva...@linux.intel.com
Link:
http://lkml.kernel.org/r/1422038748-21397-5-git-send-email-m...@codeblueprint.co.uk
Signed-off-by: Ingo Molnar mi...@kernel.org
---
arch/x86/include/asm/cpufeature.h | 9 -
arch/x86/include/asm/processor.h | 3 +++
arch/x86/kernel/cpu/common.c | 39 +++
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeature.h
b/arch/x86/include/asm/cpufeature.h
index 90a5485..361922d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
#include asm/disabled-features.h
#endif
-#define NCAPINTS 11 /* N 32-bit words worth of info */
+#define NCAPINTS 13 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -226,6 +226,7 @@
#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID( 9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM( 9*32+11) /* Restricted Transactional
Memory */
+#define X86_FEATURE_CQM( 9*32+12) /* Cache QoS Monitoring */
#define X86_FEATURE_MPX( 9*32+14) /* Memory Protection
Extension */
#define X86_FEATURE_AVX512F( 9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
@@ -242,6 +243,12 @@
#define X86_FEATURE_XGETBV1(10*32+ 2) /* XGETBV with ECX = 1 */
#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
+/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x000F:0 (edx), word 11 */
+#define X86_FEATURE_CQM_LLC(11*32+ 1) /* LLC QoS if 1 */
+
+/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x000F:1 (edx), word 12 */
+#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1
*/
+
/*
* BUG word(s)
*/
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index ec1c935..a12d50e 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -109,6 +109,9 @@ struct cpuinfo_x86 {
/* in KB - valid for CPUS which support this call: */
int x86_cache_size;
int x86_cache_alignment;/* In bytes */
+ /* Cache QoS architectural values: */
+ int x86_cache_max_rmid; /* max index */
+ int x86_cache_occ_scale;/* scale to bytes */
int x86_power;
unsigned long loops_per_jiffy;
/* cpuid returned max cores value: */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 07f2fc3..9fa00b2 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -645,6 +645,30 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c-x86_capability[10] = eax;
}
+ /* Additional Intel-defined flags: level 0x000F */
+ if (c-cpuid_level = 0x000F) {
+ u32 eax, ebx, ecx, edx;
+
+ /* QoS sub-leaf, EAX=0Fh, ECX=0 */
+ cpuid_count(0x000F,
