[tip:x86/cpufeature] x86/cpuid: Cleanup cpuid_regs definitions

2016-11-16 Thread tip-bot for He Chen 
Commit-ID:  47f10a36003eaf493125a5e6687dd1ff775bfd8c
Gitweb: http://git.kernel.org/tip/47f10a36003eaf493125a5e6687dd1ff775bfd8c
Author: He Chen 
AuthorDate: Fri, 11 Nov 2016 17:25:34 +0800
Committer:  Thomas Gleixner 
CommitDate: Wed, 16 Nov 2016 11:13:09 +0100

x86/cpuid: Cleanup cpuid_regs definitions

cpuid_regs is defined multiple times as structure and enum. Rename the enum
and move all of it to processor.h so we don't end up with more instances.

Rename the misnomed register enumeration from CR_* to the obvious CPUID_*.

[ tglx: Rewrote changelog ]

Signed-off-by: He Chen 
Reviewed-by: Borislav Petkov 
Cc: Luwei Kang 
Cc: k...@vger.kernel.org
Cc: Radim Krčmář 
Cc: Piotr Luc 
Cc: Paolo Bonzini 
Link: 
http://lkml.kernel.org/r/1478856336-9388-2-git-send-email-he.c...@linux.intel.com
Signed-off-by: Thomas Gleixner 

---
 arch/x86/events/intel/pt.c   | 45 +---
 arch/x86/include/asm/processor.h | 11 ++
 arch/x86/kernel/cpu/scattered.c  | 28 ++---
 arch/x86/kernel/cpuid.c  |  4 
 4 files changed, 41 insertions(+), 47 deletions(-)

diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index c5047b8..1c1b9fe 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -36,13 +36,6 @@ static DEFINE_PER_CPU(struct pt, pt_ctx);
 
 static struct pt_pmu pt_pmu;
 
-enum cpuid_regs {
-   CR_EAX = 0,
-   CR_ECX,
-   CR_EDX,
-   CR_EBX
-};
-
 /*
  * Capabilities of Intel PT hardware, such as number of address bits or
  * supported output schemes, are cached and exported to userspace as "caps"
@@ -64,21 +57,21 @@ static struct pt_cap_desc {
u8  reg;
u32 mask;
 } pt_caps[] = {
-   PT_CAP(max_subleaf, 0, CR_EAX, 0x),
-   PT_CAP(cr3_filtering,   0, CR_EBX, BIT(0)),
-   PT_CAP(psb_cyc, 0, CR_EBX, BIT(1)),
-   PT_CAP(ip_filtering,0, CR_EBX, BIT(2)),
-   PT_CAP(mtc, 0, CR_EBX, BIT(3)),
-   PT_CAP(ptwrite, 0, CR_EBX, BIT(4)),
-   PT_CAP(power_event_trace,   0, CR_EBX, BIT(5)),
-   PT_CAP(topa_output, 0, CR_ECX, BIT(0)),
-   PT_CAP(topa_multiple_entries,   0, CR_ECX, BIT(1)),
-   PT_CAP(single_range_output, 0, CR_ECX, BIT(2)),
-   PT_CAP(payloads_lip,0, CR_ECX, BIT(31)),
-   PT_CAP(num_address_ranges,  1, CR_EAX, 0x3),
-   PT_CAP(mtc_periods, 1, CR_EAX, 0x),
-   PT_CAP(cycle_thresholds,1, CR_EBX, 0x),
-   PT_CAP(psb_periods, 1, CR_EBX, 0x),
+   PT_CAP(max_subleaf, 0, CPUID_EAX, 0x),
+   PT_CAP(cr3_filtering,   0, CPUID_EBX, BIT(0)),
+   PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)),
+   PT_CAP(ip_filtering,0, CPUID_EBX, BIT(2)),
+   PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
+   PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
+   PT_CAP(power_event_trace,   0, CPUID_EBX, BIT(5)),
+   PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
+   PT_CAP(topa_multiple_entries,   0, CPUID_ECX, BIT(1)),
+   PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
+   PT_CAP(payloads_lip,0, CPUID_ECX, BIT(31)),
+   PT_CAP(num_address_ranges,  1, CPUID_EAX, 0x3),
+   PT_CAP(mtc_periods, 1, CPUID_EAX, 0x),
+   PT_CAP(cycle_thresholds,1, CPUID_EBX, 0x),
+   PT_CAP(psb_periods, 1, CPUID_EBX, 0x),
 };
 
 static u32 pt_cap_get(enum pt_capabilities cap)
@@ -213,10 +206,10 @@ static int __init pt_pmu_hw_init(void)
 
for (i = 0; i < PT_CPUID_LEAVES; i++) {
cpuid_count(20, i,
-   _pmu.caps[CR_EAX + i*PT_CPUID_REGS_NUM],
-   _pmu.caps[CR_EBX + i*PT_CPUID_REGS_NUM],
-   _pmu.caps[CR_ECX + i*PT_CPUID_REGS_NUM],
-   _pmu.caps[CR_EDX + i*PT_CPUID_REGS_NUM]);
+   _pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM],
+   _pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM],
+   _pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM],
+   _pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]);
}
 
ret = -ENOMEM;
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 984a7bf..8f6ac5b 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -137,6 +137,17 @@ struct cpuinfo_x86 {
u32 microcode;
 };
 
+struct cpuid_regs {
+   u32 eax, ebx, ecx, edx;
+};
+
+enum cpuid_regs_idx {
+

[tip:x86/cpufeature] x86/cpuid: Cleanup cpuid_regs definitions

2016-11-16 Thread tip-bot for He Chen 
Commit-ID:  47f10a36003eaf493125a5e6687dd1ff775bfd8c
Gitweb: http://git.kernel.org/tip/47f10a36003eaf493125a5e6687dd1ff775bfd8c
Author: He Chen 
AuthorDate: Fri, 11 Nov 2016 17:25:34 +0800
Committer:  Thomas Gleixner 
CommitDate: Wed, 16 Nov 2016 11:13:09 +0100

x86/cpuid: Cleanup cpuid_regs definitions

cpuid_regs is defined multiple times as structure and enum. Rename the enum
and move all of it to processor.h so we don't end up with more instances.

Rename the misnomed register enumeration from CR_* to the obvious CPUID_*.

[ tglx: Rewrote changelog ]

Signed-off-by: He Chen 
Reviewed-by: Borislav Petkov 
Cc: Luwei Kang 
Cc: k...@vger.kernel.org
Cc: Radim Krčmář 
Cc: Piotr Luc 
Cc: Paolo Bonzini 
Link: 
http://lkml.kernel.org/r/1478856336-9388-2-git-send-email-he.c...@linux.intel.com
Signed-off-by: Thomas Gleixner 

---
 arch/x86/events/intel/pt.c   | 45 +---
 arch/x86/include/asm/processor.h | 11 ++
 arch/x86/kernel/cpu/scattered.c  | 28 ++---
 arch/x86/kernel/cpuid.c  |  4 
 4 files changed, 41 insertions(+), 47 deletions(-)

diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index c5047b8..1c1b9fe 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -36,13 +36,6 @@ static DEFINE_PER_CPU(struct pt, pt_ctx);
 
 static struct pt_pmu pt_pmu;
 
-enum cpuid_regs {
-   CR_EAX = 0,
-   CR_ECX,
-   CR_EDX,
-   CR_EBX
-};
-
 /*
  * Capabilities of Intel PT hardware, such as number of address bits or
  * supported output schemes, are cached and exported to userspace as "caps"
@@ -64,21 +57,21 @@ static struct pt_cap_desc {
u8  reg;
u32 mask;
 } pt_caps[] = {
-   PT_CAP(max_subleaf, 0, CR_EAX, 0x),
-   PT_CAP(cr3_filtering,   0, CR_EBX, BIT(0)),
-   PT_CAP(psb_cyc, 0, CR_EBX, BIT(1)),
-   PT_CAP(ip_filtering,0, CR_EBX, BIT(2)),
-   PT_CAP(mtc, 0, CR_EBX, BIT(3)),
-   PT_CAP(ptwrite, 0, CR_EBX, BIT(4)),
-   PT_CAP(power_event_trace,   0, CR_EBX, BIT(5)),
-   PT_CAP(topa_output, 0, CR_ECX, BIT(0)),
-   PT_CAP(topa_multiple_entries,   0, CR_ECX, BIT(1)),
-   PT_CAP(single_range_output, 0, CR_ECX, BIT(2)),
-   PT_CAP(payloads_lip,0, CR_ECX, BIT(31)),
-   PT_CAP(num_address_ranges,  1, CR_EAX, 0x3),
-   PT_CAP(mtc_periods, 1, CR_EAX, 0x),
-   PT_CAP(cycle_thresholds,1, CR_EBX, 0x),
-   PT_CAP(psb_periods, 1, CR_EBX, 0x),
+   PT_CAP(max_subleaf, 0, CPUID_EAX, 0x),
+   PT_CAP(cr3_filtering,   0, CPUID_EBX, BIT(0)),
+   PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)),
+   PT_CAP(ip_filtering,0, CPUID_EBX, BIT(2)),
+   PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
+   PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
+   PT_CAP(power_event_trace,   0, CPUID_EBX, BIT(5)),
+   PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
+   PT_CAP(topa_multiple_entries,   0, CPUID_ECX, BIT(1)),
+   PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
+   PT_CAP(payloads_lip,0, CPUID_ECX, BIT(31)),
+   PT_CAP(num_address_ranges,  1, CPUID_EAX, 0x3),
+   PT_CAP(mtc_periods, 1, CPUID_EAX, 0x),
+   PT_CAP(cycle_thresholds,1, CPUID_EBX, 0x),
+   PT_CAP(psb_periods, 1, CPUID_EBX, 0x),
 };
 
 static u32 pt_cap_get(enum pt_capabilities cap)
@@ -213,10 +206,10 @@ static int __init pt_pmu_hw_init(void)
 
for (i = 0; i < PT_CPUID_LEAVES; i++) {
cpuid_count(20, i,
-   _pmu.caps[CR_EAX + i*PT_CPUID_REGS_NUM],
-   _pmu.caps[CR_EBX + i*PT_CPUID_REGS_NUM],
-   _pmu.caps[CR_ECX + i*PT_CPUID_REGS_NUM],
-   _pmu.caps[CR_EDX + i*PT_CPUID_REGS_NUM]);
+   _pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM],
+   _pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM],
+   _pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM],
+   _pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]);
}
 
ret = -ENOMEM;
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 984a7bf..8f6ac5b 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -137,6 +137,17 @@ struct cpuinfo_x86 {
u32 microcode;
 };
 
+struct cpuid_regs {
+   u32 eax, ebx, ecx, edx;
+};
+
+enum cpuid_regs_idx {
+   CPUID_EAX = 0,
+   CPUID_EBX,
+   CPUID_ECX,
+   CPUID_EDX,
+};
+
 #define X86_VENDOR_INTEL   0
 #define X86_VENDOR_CYRIX   1
 #define X86_VENDOR_AMD 2
diff --git