Re: [v2,2/3] PCI: mediatek: Add new generation controller support
On Mon, 2020-09-14 at 08:32 -0600, Rob Herring wrote: > On Mon, Sep 14, 2020 at 5:07 AM Jianjun Wang > wrote: > > > > On Fri, 2020-09-11 at 16:44 -0600, Rob Herring wrote: > > > On Thu, Sep 10, 2020 at 11:45:35AM +0800, Jianjun Wang wrote: > > > > MediaTek's PCIe host controller has three generation HWs, the new > > > > generation HW is an individual bridge, it supoorts Gen3 speed and > > > > up to 256 MSI interrupt numbers for multi-function devices. > > > > > > > > Add support for new Gen3 controller which can be found on MT8192. > > > > > > > > Signed-off-by: Jianjun Wang > > > > Acked-by: Ryder Lee > > > > --- > > > > drivers/pci/controller/Kconfig | 14 + > > > > drivers/pci/controller/Makefile |1 + > > > > drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++ > > > > 3 files changed, 1091 insertions(+) > > > > create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c > > > > > > > > diff --git a/drivers/pci/controller/Kconfig > > > > b/drivers/pci/controller/Kconfig > > > > index f18c3725ef80..83daa772595b 100644 > > > > --- a/drivers/pci/controller/Kconfig > > > > +++ b/drivers/pci/controller/Kconfig > > > > @@ -239,6 +239,20 @@ config PCIE_MEDIATEK > > > > Say Y here if you want to enable PCIe controller support on > > > > MediaTek SoCs. > > > > > > > > +config PCIE_MEDIATEK_GEN3 > > > > + tristate "MediaTek GEN3 PCIe controller" > > > > + depends on ARCH_MEDIATEK || COMPILE_TEST > > > > + depends on OF > > > > + depends on PCI_MSI_IRQ_DOMAIN > > > > + help > > > > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. > > > > + This PCIe controller provides the capable of Gen3, Gen2 and > > > > + Gen1 speed, and support up to 256 MSI interrupt numbers for > > > > + multi-function devices. > > > > + > > > > + Say Y here if you want to enable Gen3 PCIe controller support on > > > > + MediaTek SoCs. > > > > + > > > > config PCIE_TANGO_SMP8759 > > > > bool "Tango SMP8759 PCIe controller (DANGEROUS)" > > > > depends on ARCH_TANGO && PCI_MSI && OF > > > > diff --git a/drivers/pci/controller/Makefile > > > > b/drivers/pci/controller/Makefile > > > > index bcdbf49ab1e4..9c1b96777597 100644 > > > > --- a/drivers/pci/controller/Makefile > > > > +++ b/drivers/pci/controller/Makefile > > > > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o > > > > obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o > > > > obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o > > > > obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o > > > > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o > > > > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o > > > > obj-$(CONFIG_VMD) += vmd.o > > > > obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o > > > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c > > > > b/drivers/pci/controller/pcie-mediatek-gen3.c > > > > new file mode 100644 > > > > index ..f8c8bdf88d33 > > > > --- /dev/null > > > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > > > @@ -0,0 +1,1076 @@ > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > +/* > > > > + * MediaTek PCIe host controller driver. > > > > + * > > > > + * Copyright (c) 2020 MediaTek Inc. > > > > + * Author: Jianjun Wang > > > > + */ > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +#include "../pci.h" > > > > + > > > > +#define PCIE_SETTING_REG 0x80 > > > > +#define PCIE_PCI_IDS_1 0x9c > > > > +#define PCI_CLASS(class) (class << 8) > > > > +#define PCIE_RC_MODE BIT(0) > > > > + > > > > +#define PCIE_CFGNUM_REG0x140 > > > > +#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) > > > > +#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) > > > > +#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & > > > > GENMASK(19, 16)) > > > > +#define PCIE_CFG_FORCE_BYTE_EN BIT(20) > > > > +#define PCIE_CFG_OFFSET_ADDR 0x1000 > > > > +#define PCIE_CFG_HEADER(devfn, bus) \ > > > > + (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus)) > > > > + > > > > +#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \ > > > > + (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \ > > > > +| PCIE_CFG_FORCE_BYTE_EN) > > > > + > > > > +#define PCIE_RST_CTRL_REG 0x148 > > > > +#define PCIE_MAC_RSTB BIT(0) > > > > +#define PCIE_PHY_RSTB BIT(1) > > > > +#define PCIE_BRG_RSTB BIT(2) > > > > +#define PCIE_PE_RSTB BIT(3) > > > > + > >
Re: [v2,2/3] PCI: mediatek: Add new generation controller support
On Mon, Sep 14, 2020 at 5:07 AM Jianjun Wang wrote: > > On Fri, 2020-09-11 at 16:44 -0600, Rob Herring wrote: > > On Thu, Sep 10, 2020 at 11:45:35AM +0800, Jianjun Wang wrote: > > > MediaTek's PCIe host controller has three generation HWs, the new > > > generation HW is an individual bridge, it supoorts Gen3 speed and > > > up to 256 MSI interrupt numbers for multi-function devices. > > > > > > Add support for new Gen3 controller which can be found on MT8192. > > > > > > Signed-off-by: Jianjun Wang > > > Acked-by: Ryder Lee > > > --- > > > drivers/pci/controller/Kconfig | 14 + > > > drivers/pci/controller/Makefile |1 + > > > drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++ > > > 3 files changed, 1091 insertions(+) > > > create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c > > > > > > diff --git a/drivers/pci/controller/Kconfig > > > b/drivers/pci/controller/Kconfig > > > index f18c3725ef80..83daa772595b 100644 > > > --- a/drivers/pci/controller/Kconfig > > > +++ b/drivers/pci/controller/Kconfig > > > @@ -239,6 +239,20 @@ config PCIE_MEDIATEK > > > Say Y here if you want to enable PCIe controller support on > > > MediaTek SoCs. > > > > > > +config PCIE_MEDIATEK_GEN3 > > > + tristate "MediaTek GEN3 PCIe controller" > > > + depends on ARCH_MEDIATEK || COMPILE_TEST > > > + depends on OF > > > + depends on PCI_MSI_IRQ_DOMAIN > > > + help > > > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. > > > + This PCIe controller provides the capable of Gen3, Gen2 and > > > + Gen1 speed, and support up to 256 MSI interrupt numbers for > > > + multi-function devices. > > > + > > > + Say Y here if you want to enable Gen3 PCIe controller support on > > > + MediaTek SoCs. > > > + > > > config PCIE_TANGO_SMP8759 > > > bool "Tango SMP8759 PCIe controller (DANGEROUS)" > > > depends on ARCH_TANGO && PCI_MSI && OF > > > diff --git a/drivers/pci/controller/Makefile > > > b/drivers/pci/controller/Makefile > > > index bcdbf49ab1e4..9c1b96777597 100644 > > > --- a/drivers/pci/controller/Makefile > > > +++ b/drivers/pci/controller/Makefile > > > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o > > > obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o > > > obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o > > > obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o > > > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o > > > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o > > > obj-$(CONFIG_VMD) += vmd.o > > > obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o > > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c > > > b/drivers/pci/controller/pcie-mediatek-gen3.c > > > new file mode 100644 > > > index ..f8c8bdf88d33 > > > --- /dev/null > > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > > @@ -0,0 +1,1076 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * MediaTek PCIe host controller driver. > > > + * > > > + * Copyright (c) 2020 MediaTek Inc. > > > + * Author: Jianjun Wang > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#include "../pci.h" > > > + > > > +#define PCIE_SETTING_REG 0x80 > > > +#define PCIE_PCI_IDS_1 0x9c > > > +#define PCI_CLASS(class) (class << 8) > > > +#define PCIE_RC_MODE BIT(0) > > > + > > > +#define PCIE_CFGNUM_REG0x140 > > > +#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) > > > +#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) > > > +#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & > > > GENMASK(19, 16)) > > > +#define PCIE_CFG_FORCE_BYTE_EN BIT(20) > > > +#define PCIE_CFG_OFFSET_ADDR 0x1000 > > > +#define PCIE_CFG_HEADER(devfn, bus) \ > > > + (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus)) > > > + > > > +#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \ > > > + (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \ > > > +| PCIE_CFG_FORCE_BYTE_EN) > > > + > > > +#define PCIE_RST_CTRL_REG 0x148 > > > +#define PCIE_MAC_RSTB BIT(0) > > > +#define PCIE_PHY_RSTB BIT(1) > > > +#define PCIE_BRG_RSTB BIT(2) > > > +#define PCIE_PE_RSTB BIT(3) > > > + > > > +#define PCIE_MISC_STATUS_REG 0x14C > > > +#define PCIE_LTR_MSG_RECEIVED BIT(0) > > > +#define PCIE_PCIE_MSG_RECEIVED BIT(1) > > > + > > > +#define PCIE_LTSSM_STATUS_REG 0x150 > > > +#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24)
Re: [v2,2/3] PCI: mediatek: Add new generation controller support
On Fri, 2020-09-11 at 16:44 -0600, Rob Herring wrote: > On Thu, Sep 10, 2020 at 11:45:35AM +0800, Jianjun Wang wrote: > > MediaTek's PCIe host controller has three generation HWs, the new > > generation HW is an individual bridge, it supoorts Gen3 speed and > > up to 256 MSI interrupt numbers for multi-function devices. > > > > Add support for new Gen3 controller which can be found on MT8192. > > > > Signed-off-by: Jianjun Wang > > Acked-by: Ryder Lee > > --- > > drivers/pci/controller/Kconfig | 14 + > > drivers/pci/controller/Makefile |1 + > > drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++ > > 3 files changed, 1091 insertions(+) > > create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c > > > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > > index f18c3725ef80..83daa772595b 100644 > > --- a/drivers/pci/controller/Kconfig > > +++ b/drivers/pci/controller/Kconfig > > @@ -239,6 +239,20 @@ config PCIE_MEDIATEK > > Say Y here if you want to enable PCIe controller support on > > MediaTek SoCs. > > > > +config PCIE_MEDIATEK_GEN3 > > + tristate "MediaTek GEN3 PCIe controller" > > + depends on ARCH_MEDIATEK || COMPILE_TEST > > + depends on OF > > + depends on PCI_MSI_IRQ_DOMAIN > > + help > > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. > > + This PCIe controller provides the capable of Gen3, Gen2 and > > + Gen1 speed, and support up to 256 MSI interrupt numbers for > > + multi-function devices. > > + > > + Say Y here if you want to enable Gen3 PCIe controller support on > > + MediaTek SoCs. > > + > > config PCIE_TANGO_SMP8759 > > bool "Tango SMP8759 PCIe controller (DANGEROUS)" > > depends on ARCH_TANGO && PCI_MSI && OF > > diff --git a/drivers/pci/controller/Makefile > > b/drivers/pci/controller/Makefile > > index bcdbf49ab1e4..9c1b96777597 100644 > > --- a/drivers/pci/controller/Makefile > > +++ b/drivers/pci/controller/Makefile > > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o > > obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o > > obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o > > obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o > > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o > > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o > > obj-$(CONFIG_VMD) += vmd.o > > obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c > > b/drivers/pci/controller/pcie-mediatek-gen3.c > > new file mode 100644 > > index ..f8c8bdf88d33 > > --- /dev/null > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > @@ -0,0 +1,1076 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * MediaTek PCIe host controller driver. > > + * > > + * Copyright (c) 2020 MediaTek Inc. > > + * Author: Jianjun Wang > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "../pci.h" > > + > > +#define PCIE_SETTING_REG 0x80 > > +#define PCIE_PCI_IDS_1 0x9c > > +#define PCI_CLASS(class) (class << 8) > > +#define PCIE_RC_MODE BIT(0) > > + > > +#define PCIE_CFGNUM_REG0x140 > > +#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) > > +#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) > > +#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, > > 16)) > > +#define PCIE_CFG_FORCE_BYTE_EN BIT(20) > > +#define PCIE_CFG_OFFSET_ADDR 0x1000 > > +#define PCIE_CFG_HEADER(devfn, bus) \ > > + (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus)) > > + > > +#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \ > > + (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \ > > +| PCIE_CFG_FORCE_BYTE_EN) > > + > > +#define PCIE_RST_CTRL_REG 0x148 > > +#define PCIE_MAC_RSTB BIT(0) > > +#define PCIE_PHY_RSTB BIT(1) > > +#define PCIE_BRG_RSTB BIT(2) > > +#define PCIE_PE_RSTB BIT(3) > > + > > +#define PCIE_MISC_STATUS_REG 0x14C > > +#define PCIE_LTR_MSG_RECEIVED BIT(0) > > +#define PCIE_PCIE_MSG_RECEIVED BIT(1) > > + > > +#define PCIE_LTSSM_STATUS_REG 0x150 > > +#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24) > > +#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) > > >> 24) > > +#define PCIE_LTSSM_STATE_L00x10 > > +#define PCIE_LTSSM_STATE_L1_IDLE 0x13 > > +#define PCIE_LTSSM_STATE_L2_IDLE 0x14 > > + > > +#define PCIE_LINK_STATUS_REG 0x154 > >
Re: [v2,2/3] PCI: mediatek: Add new generation controller support
On Fri, 2020-09-11 at 16:33 +0200, Philipp Zabel wrote:
> Hi Jianjun,
>
> On Thu, 2020-09-10 at 11:45 +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> >
> > Add support for new Gen3 controller which can be found on MT8192.
> >
> > Signed-off-by: Jianjun Wang
> > Acked-by: Ryder Lee
> > ---
> > drivers/pci/controller/Kconfig | 14 +
> > drivers/pci/controller/Makefile |1 +
> > drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++
> > 3 files changed, 1091 insertions(+)
> > create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> >
> [...]
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..f8c8bdf88d33
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> [...]
> > +static int mtk_pcie_power_up(struct mtk_pcie_port *port)
> > +{
> > + struct device *dev = port->dev;
> > + int err;
> > +
> > + port->phy_reset = devm_reset_control_get_optional(dev, "phy-rst");
>
> Please use devm_reset_control_get_optional_exclusive() instead.
>
> > + if (PTR_ERR(port->phy_reset) == -EPROBE_DEFER)
> > + return PTR_ERR(port->phy_reset);
>
> This should be
>
> if (IS_ERR(port->phy_reset))
> return PTR_ERR(port->phy_reset);
>
> there is no reason to continue if this throws -ENOMEM, for example.
>
> regards
> Philipp
Thanks for your review, I will fix it in the next version.
Re: [v2,2/3] PCI: mediatek: Add new generation controller support
On Thu, Sep 10, 2020 at 11:45:35AM +0800, Jianjun Wang wrote: > MediaTek's PCIe host controller has three generation HWs, the new > generation HW is an individual bridge, it supoorts Gen3 speed and > up to 256 MSI interrupt numbers for multi-function devices. > > Add support for new Gen3 controller which can be found on MT8192. > > Signed-off-by: Jianjun Wang > Acked-by: Ryder Lee > --- > drivers/pci/controller/Kconfig | 14 + > drivers/pci/controller/Makefile |1 + > drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++ > 3 files changed, 1091 insertions(+) > create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > index f18c3725ef80..83daa772595b 100644 > --- a/drivers/pci/controller/Kconfig > +++ b/drivers/pci/controller/Kconfig > @@ -239,6 +239,20 @@ config PCIE_MEDIATEK > Say Y here if you want to enable PCIe controller support on > MediaTek SoCs. > > +config PCIE_MEDIATEK_GEN3 > + tristate "MediaTek GEN3 PCIe controller" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + depends on OF > + depends on PCI_MSI_IRQ_DOMAIN > + help > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. > + This PCIe controller provides the capable of Gen3, Gen2 and > + Gen1 speed, and support up to 256 MSI interrupt numbers for > + multi-function devices. > + > + Say Y here if you want to enable Gen3 PCIe controller support on > + MediaTek SoCs. > + > config PCIE_TANGO_SMP8759 > bool "Tango SMP8759 PCIe controller (DANGEROUS)" > depends on ARCH_TANGO && PCI_MSI && OF > diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile > index bcdbf49ab1e4..9c1b96777597 100644 > --- a/drivers/pci/controller/Makefile > +++ b/drivers/pci/controller/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o > obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o > obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o > obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o > obj-$(CONFIG_VMD) += vmd.o > obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c > b/drivers/pci/controller/pcie-mediatek-gen3.c > new file mode 100644 > index ..f8c8bdf88d33 > --- /dev/null > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -0,0 +1,1076 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * MediaTek PCIe host controller driver. > + * > + * Copyright (c) 2020 MediaTek Inc. > + * Author: Jianjun Wang > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "../pci.h" > + > +#define PCIE_SETTING_REG 0x80 > +#define PCIE_PCI_IDS_1 0x9c > +#define PCI_CLASS(class) (class << 8) > +#define PCIE_RC_MODE BIT(0) > + > +#define PCIE_CFGNUM_REG 0x140 > +#define PCIE_CFG_DEVFN(devfn)((devfn) & GENMASK(7, 0)) > +#define PCIE_CFG_BUS(bus)(((bus) << 8) & GENMASK(15, 8)) > +#define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, > 16)) > +#define PCIE_CFG_FORCE_BYTE_EN BIT(20) > +#define PCIE_CFG_OFFSET_ADDR 0x1000 > +#define PCIE_CFG_HEADER(devfn, bus) \ > + (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus)) > + > +#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \ > + (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \ > + | PCIE_CFG_FORCE_BYTE_EN) > + > +#define PCIE_RST_CTRL_REG0x148 > +#define PCIE_MAC_RSTBBIT(0) > +#define PCIE_PHY_RSTBBIT(1) > +#define PCIE_BRG_RSTBBIT(2) > +#define PCIE_PE_RSTB BIT(3) > + > +#define PCIE_MISC_STATUS_REG 0x14C > +#define PCIE_LTR_MSG_RECEIVEDBIT(0) > +#define PCIE_PCIE_MSG_RECEIVED BIT(1) > + > +#define PCIE_LTSSM_STATUS_REG0x150 > +#define PCIE_LTSSM_STATE_MASKGENMASK(28, 24) > +#define PCIE_LTSSM_STATE(val)((val & PCIE_LTSSM_STATE_MASK) > >> 24) > +#define PCIE_LTSSM_STATE_L0 0x10 > +#define PCIE_LTSSM_STATE_L1_IDLE 0x13 > +#define PCIE_LTSSM_STATE_L2_IDLE 0x14 > + > +#define PCIE_LINK_STATUS_REG 0x154 > +#define PCIE_PORT_LINKUP BIT(8) > + > +#define PCIE_MSI_SET_NUM 8 > +#define PCIE_MSI_IRQS_PER_SET32 > +#define PCIE_MSI_IRQS_NUM \ > + (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM)) > + > +#define PCIE_INT_ENABLE_REG 0x180 >
Re: [v2,2/3] PCI: mediatek: Add new generation controller support
Hi Jianjun,
On Thu, 2020-09-10 at 11:45 +0800, Jianjun Wang wrote:
> MediaTek's PCIe host controller has three generation HWs, the new
> generation HW is an individual bridge, it supoorts Gen3 speed and
> up to 256 MSI interrupt numbers for multi-function devices.
>
> Add support for new Gen3 controller which can be found on MT8192.
>
> Signed-off-by: Jianjun Wang
> Acked-by: Ryder Lee
> ---
> drivers/pci/controller/Kconfig | 14 +
> drivers/pci/controller/Makefile |1 +
> drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++
> 3 files changed, 1091 insertions(+)
> create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
>
[...]
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> b/drivers/pci/controller/pcie-mediatek-gen3.c
> new file mode 100644
> index ..f8c8bdf88d33
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
[...]
> +static int mtk_pcie_power_up(struct mtk_pcie_port *port)
> +{
> + struct device *dev = port->dev;
> + int err;
> +
> + port->phy_reset = devm_reset_control_get_optional(dev, "phy-rst");
Please use devm_reset_control_get_optional_exclusive() instead.
> + if (PTR_ERR(port->phy_reset) == -EPROBE_DEFER)
> + return PTR_ERR(port->phy_reset);
This should be
if (IS_ERR(port->phy_reset))
return PTR_ERR(port->phy_reset);
there is no reason to continue if this throws -ENOMEM, for example.
regards
Philipp
[v2,2/3] PCI: mediatek: Add new generation controller support
MediaTek's PCIe host controller has three generation HWs, the new generation HW is an individual bridge, it supoorts Gen3 speed and up to 256 MSI interrupt numbers for multi-function devices. Add support for new Gen3 controller which can be found on MT8192. Signed-off-by: Jianjun Wang Acked-by: Ryder Lee --- drivers/pci/controller/Kconfig | 14 + drivers/pci/controller/Makefile |1 + drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++ 3 files changed, 1091 insertions(+) create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index f18c3725ef80..83daa772595b 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -239,6 +239,20 @@ config PCIE_MEDIATEK Say Y here if you want to enable PCIe controller support on MediaTek SoCs. +config PCIE_MEDIATEK_GEN3 + tristate "MediaTek GEN3 PCIe controller" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + depends on PCI_MSI_IRQ_DOMAIN + help + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. + This PCIe controller provides the capable of Gen3, Gen2 and + Gen1 speed, and support up to 256 MSI interrupt numbers for + multi-function devices. + + Say Y here if you want to enable Gen3 PCIe controller support on + MediaTek SoCs. + config PCIE_TANGO_SMP8759 bool "Tango SMP8759 PCIe controller (DANGEROUS)" depends on ARCH_TANGO && PCI_MSI && OF diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index bcdbf49ab1e4..9c1b96777597 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o obj-$(CONFIG_VMD) += vmd.o obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c new file mode 100644 index ..f8c8bdf88d33 --- /dev/null +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -0,0 +1,1076 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek PCIe host controller driver. + * + * Copyright (c) 2020 MediaTek Inc. + * Author: Jianjun Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +#define PCIE_SETTING_REG 0x80 +#define PCIE_PCI_IDS_1 0x9c +#define PCI_CLASS(class) (class << 8) +#define PCIE_RC_MODE BIT(0) + +#define PCIE_CFGNUM_REG0x140 +#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) +#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) +#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 16)) +#define PCIE_CFG_FORCE_BYTE_EN BIT(20) +#define PCIE_CFG_OFFSET_ADDR 0x1000 +#define PCIE_CFG_HEADER(devfn, bus) \ + (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus)) + +#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \ + (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \ +| PCIE_CFG_FORCE_BYTE_EN) + +#define PCIE_RST_CTRL_REG 0x148 +#define PCIE_MAC_RSTB BIT(0) +#define PCIE_PHY_RSTB BIT(1) +#define PCIE_BRG_RSTB BIT(2) +#define PCIE_PE_RSTB BIT(3) + +#define PCIE_MISC_STATUS_REG 0x14C +#define PCIE_LTR_MSG_RECEIVED BIT(0) +#define PCIE_PCIE_MSG_RECEIVED BIT(1) + +#define PCIE_LTSSM_STATUS_REG 0x150 +#define PCIE_LTSSM_STATE_MASK GENMASK(28, 24) +#define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24) +#define PCIE_LTSSM_STATE_L00x10 +#define PCIE_LTSSM_STATE_L1_IDLE 0x13 +#define PCIE_LTSSM_STATE_L2_IDLE 0x14 + +#define PCIE_LINK_STATUS_REG 0x154 +#define PCIE_PORT_LINKUP BIT(8) + +#define PCIE_MSI_SET_NUM 8 +#define PCIE_MSI_IRQS_PER_SET 32 +#define PCIE_MSI_IRQS_NUM \ + (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM)) + +#define PCIE_INT_ENABLE_REG0x180 +#define PCIE_MSI_MASK GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8) +#define PCIE_MSI_SHIFT 8 +#define PCIE_INTX_SHIFT24 +#define PCIE_INTX_MASK GENMASK(27, 24) +#define PCIE_MSG_MASK BIT(28) +#define PCIE_AER_MASK BIT(29) +#define
