Re: [v2] PCI: Avoid unsync of LTR mechanism configuration
On Thu, 2021-01-28 at 16:27 +0200, Mika Westerberg wrote: > Hi, > > On Thu, Jan 28, 2021 at 06:05:31PM +0800, mingchuang.q...@mediatek.com wrote: > > From: Mingchuang Qiao > > > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is > > configured in pci_configure_ltr(). If device and bridge both support LTR > > mechanism, the "LTR Mechanism Enable" bit of device and bridge will be > > enabled in DEVCTL2 register. And pci_dev->ltr_path will be set as 1. > > > > If PCIe link goes down when device resets, the "LTR Mechanism Enable" bit > > of bridge will change to 0 according to PCIe r5.0, sec 7.5.3.16. However, > > the pci_dev->ltr_path value of bridge is still 1. > > > > For following conditions, check and re-configure "LTR Mechanism Enable" bit > > of bridge to make "LTR Mechanism Enable" bit mtach ltr_path value. > >-before configuring device's LTR for hot-remove/hot-add > >-before restoring device's DEVCTL2 register when restore device state > > > > Signed-off-by: Mingchuang Qiao > > --- > > changes of v2 > > -modify patch description > > -reconfigure bridge's LTR before restoring device DEVCTL2 register > > --- > > drivers/pci/pci.c | 25 + > > drivers/pci/probe.c | 19 --- > > 2 files changed, 41 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > > index b9fecc25d213..88b4eb70c252 100644 > > --- a/drivers/pci/pci.c > > +++ b/drivers/pci/pci.c > > @@ -1437,6 +1437,24 @@ static int pci_save_pcie_state(struct pci_dev *dev) > > return 0; > > } > > > > +static void pci_reconfigure_bridge_ltr(struct pci_dev *dev) > > +{ > > +#ifdef CONFIG_PCIEASPM > > + struct pci_dev *bridge; > > + u32 ctl; > > + > > + bridge = pci_upstream_bridge(dev); > > + if (bridge && bridge->ltr_path) { > > + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, ); > > + if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { > > + pci_dbg(bridge, "re-enabling LTR\n"); > > + pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, > > +PCI_EXP_DEVCTL2_LTR_EN); > > + } > > + } > > +#endif > > +} > > + > > static void pci_restore_pcie_state(struct pci_dev *dev) > > { > > int i = 0; > > @@ -1447,6 +1465,13 @@ static void pci_restore_pcie_state(struct pci_dev > > *dev) > > if (!save_state) > > return; > > > > + /* > > +* Downstream ports reset the LTR enable bit when link goes down. > > +* Check and re-configure the bit here before restoring device. > > +* PCIe r5.0, sec 7.5.3.16. > > +*/ > > + pci_reconfigure_bridge_ltr(dev); > > + > > cap = (u16 *)_state->cap.data[0]; > > pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); > > pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > > index 953f15abc850..4ad172517fd2 100644 > > --- a/drivers/pci/probe.c > > +++ b/drivers/pci/probe.c > > @@ -2132,9 +2132,22 @@ static void pci_configure_ltr(struct pci_dev *dev) > > * Complex and all intermediate Switches indicate support for LTR. > > * PCIe r4.0, sec 6.18. > > */ > > - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || > > - ((bridge = pci_upstream_bridge(dev)) && > > - bridge->ltr_path)) { > > + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { > > + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, > > +PCI_EXP_DEVCTL2_LTR_EN); > > + dev->ltr_path = 1; > > + return; > > + } > > + > > + bridge = pci_upstream_bridge(dev); > > + if (bridge && bridge->ltr_path) { > > + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, ); > > + if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { > > + pci_dbg(bridge, "re-enabling LTR\n"); > > + pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, > > +PCI_EXP_DEVCTL2_LTR_EN); > > + } > > + > > Can't you use pci_reconfigure_bridge_ltr() here too? > > Otherwise looks good. Thanks for review. I have sent a new patch for this. https://lore.kernel.org/linux-arm-kernel/20210129071137.8743-1-mingchuang.q...@mediatek.com/
Re: [v2] PCI: Avoid unsync of LTR mechanism configuration
Hi, On Thu, Jan 28, 2021 at 06:05:31PM +0800, mingchuang.q...@mediatek.com wrote: > From: Mingchuang Qiao > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is > configured in pci_configure_ltr(). If device and bridge both support LTR > mechanism, the "LTR Mechanism Enable" bit of device and bridge will be > enabled in DEVCTL2 register. And pci_dev->ltr_path will be set as 1. > > If PCIe link goes down when device resets, the "LTR Mechanism Enable" bit > of bridge will change to 0 according to PCIe r5.0, sec 7.5.3.16. However, > the pci_dev->ltr_path value of bridge is still 1. > > For following conditions, check and re-configure "LTR Mechanism Enable" bit > of bridge to make "LTR Mechanism Enable" bit mtach ltr_path value. >-before configuring device's LTR for hot-remove/hot-add >-before restoring device's DEVCTL2 register when restore device state > > Signed-off-by: Mingchuang Qiao > --- > changes of v2 > -modify patch description > -reconfigure bridge's LTR before restoring device DEVCTL2 register > --- > drivers/pci/pci.c | 25 + > drivers/pci/probe.c | 19 --- > 2 files changed, 41 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index b9fecc25d213..88b4eb70c252 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -1437,6 +1437,24 @@ static int pci_save_pcie_state(struct pci_dev *dev) > return 0; > } > > +static void pci_reconfigure_bridge_ltr(struct pci_dev *dev) > +{ > +#ifdef CONFIG_PCIEASPM > + struct pci_dev *bridge; > + u32 ctl; > + > + bridge = pci_upstream_bridge(dev); > + if (bridge && bridge->ltr_path) { > + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, ); > + if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { > + pci_dbg(bridge, "re-enabling LTR\n"); > + pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, > + PCI_EXP_DEVCTL2_LTR_EN); > + } > + } > +#endif > +} > + > static void pci_restore_pcie_state(struct pci_dev *dev) > { > int i = 0; > @@ -1447,6 +1465,13 @@ static void pci_restore_pcie_state(struct pci_dev *dev) > if (!save_state) > return; > > + /* > + * Downstream ports reset the LTR enable bit when link goes down. > + * Check and re-configure the bit here before restoring device. > + * PCIe r5.0, sec 7.5.3.16. > + */ > + pci_reconfigure_bridge_ltr(dev); > + > cap = (u16 *)_state->cap.data[0]; > pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); > pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 953f15abc850..4ad172517fd2 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -2132,9 +2132,22 @@ static void pci_configure_ltr(struct pci_dev *dev) >* Complex and all intermediate Switches indicate support for LTR. >* PCIe r4.0, sec 6.18. >*/ > - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || > - ((bridge = pci_upstream_bridge(dev)) && > - bridge->ltr_path)) { > + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { > + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, > + PCI_EXP_DEVCTL2_LTR_EN); > + dev->ltr_path = 1; > + return; > + } > + > + bridge = pci_upstream_bridge(dev); > + if (bridge && bridge->ltr_path) { > + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, ); > + if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { > + pci_dbg(bridge, "re-enabling LTR\n"); > + pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, > + PCI_EXP_DEVCTL2_LTR_EN); > + } > + Can't you use pci_reconfigure_bridge_ltr() here too? Otherwise looks good.
[v2] PCI: Avoid unsync of LTR mechanism configuration
From: Mingchuang Qiao In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is configured in pci_configure_ltr(). If device and bridge both support LTR mechanism, the "LTR Mechanism Enable" bit of device and bridge will be enabled in DEVCTL2 register. And pci_dev->ltr_path will be set as 1. If PCIe link goes down when device resets, the "LTR Mechanism Enable" bit of bridge will change to 0 according to PCIe r5.0, sec 7.5.3.16. However, the pci_dev->ltr_path value of bridge is still 1. For following conditions, check and re-configure "LTR Mechanism Enable" bit of bridge to make "LTR Mechanism Enable" bit mtach ltr_path value. -before configuring device's LTR for hot-remove/hot-add -before restoring device's DEVCTL2 register when restore device state Signed-off-by: Mingchuang Qiao --- changes of v2 -modify patch description -reconfigure bridge's LTR before restoring device DEVCTL2 register --- drivers/pci/pci.c | 25 + drivers/pci/probe.c | 19 --- 2 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b9fecc25d213..88b4eb70c252 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1437,6 +1437,24 @@ static int pci_save_pcie_state(struct pci_dev *dev) return 0; } +static void pci_reconfigure_bridge_ltr(struct pci_dev *dev) +{ +#ifdef CONFIG_PCIEASPM + struct pci_dev *bridge; + u32 ctl; + + bridge = pci_upstream_bridge(dev); + if (bridge && bridge->ltr_path) { + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, ); + if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { + pci_dbg(bridge, "re-enabling LTR\n"); + pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, +PCI_EXP_DEVCTL2_LTR_EN); + } + } +#endif +} + static void pci_restore_pcie_state(struct pci_dev *dev) { int i = 0; @@ -1447,6 +1465,13 @@ static void pci_restore_pcie_state(struct pci_dev *dev) if (!save_state) return; + /* +* Downstream ports reset the LTR enable bit when link goes down. +* Check and re-configure the bit here before restoring device. +* PCIe r5.0, sec 7.5.3.16. +*/ + pci_reconfigure_bridge_ltr(dev); + cap = (u16 *)_state->cap.data[0]; pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 953f15abc850..4ad172517fd2 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2132,9 +2132,22 @@ static void pci_configure_ltr(struct pci_dev *dev) * Complex and all intermediate Switches indicate support for LTR. * PCIe r4.0, sec 6.18. */ - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || - ((bridge = pci_upstream_bridge(dev)) && - bridge->ltr_path)) { + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, +PCI_EXP_DEVCTL2_LTR_EN); + dev->ltr_path = 1; + return; + } + + bridge = pci_upstream_bridge(dev); + if (bridge && bridge->ltr_path) { + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, ); + if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { + pci_dbg(bridge, "re-enabling LTR\n"); + pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, +PCI_EXP_DEVCTL2_LTR_EN); + } + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); dev->ltr_path = 1; -- 2.18.0