Re: [v7,4/7] PCI: mediatek-gen3: Add INTx support
On Tue, 2021-01-26 at 12:25 +, Marc Zyngier wrote:
> On 2021-01-13 11:39, Jianjun Wang wrote:
> > Add INTx support for MediaTek Gen3 PCIe controller.
> >
> > Signed-off-by: Jianjun Wang
> > Acked-by: Ryder Lee
> > ---
> > drivers/pci/controller/pcie-mediatek-gen3.c | 163
> > 1 file changed, 163 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index c00ea7c167de..7979a2856c35 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -9,6 +9,9 @@
> > #include
> > #include
> > #include
> > +#include
> > +#include
> > +#include
> > #include
> > #include
> > #include
> > @@ -49,6 +52,12 @@
> > #define PCIE_LINK_STATUS_REG 0x154
> > #define PCIE_PORT_LINKUP BIT(8)
> >
> > +#define PCIE_INT_ENABLE_REG0x180
> > +#define PCIE_INTX_SHIFT24
> > +#define PCIE_INTX_MASK GENMASK(27, 24)
>
> I guess this '24' is actually PCIE_INTX_SHIFT? In this case,
> please write it as
>
> GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
>
> to make it clear that you are dealing with one bit per INTx.
Yes, I will fix it in the next version, thanks for your review.
>
> > +
> > +#define PCIE_INT_STATUS_REG0x184
> > +
> > #define PCIE_TRANS_TABLE_BASE_REG 0x800
> > #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
> > #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
> > @@ -77,6 +86,8 @@
> > * @phy: PHY controller block
> > * @clks: PCIe clocks
> > * @num_clks: PCIe clocks count for this port
> > + * @irq: PCIe controller interrupt number
> > + * @intx_domain: legacy INTx IRQ domain
> > */
> > struct mtk_pcie_port {
> > struct device *dev;
> > @@ -87,6 +98,9 @@ struct mtk_pcie_port {
> > struct phy *phy;
> > struct clk_bulk_data *clks;
> > int num_clks;
> > +
> > + int irq;
> > + struct irq_domain *intx_domain;
> > };
> >
> > /**
> > @@ -266,6 +280,149 @@ static int mtk_pcie_startup_port(struct
> > mtk_pcie_port *port)
> > return 0;
> > }
> >
> > +static int mtk_pcie_set_affinity(struct irq_data *data,
> > +const struct cpumask *mask, bool force)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static void mtk_intx_mask(struct irq_data *data)
> > +{
> > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > + u32 val;
> > +
> > + val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
> > + val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
> > + writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
>
> This is missing some locking. Otherwise, two concurrent mask/unmask
> for different interrupts will corrupt each other's state.
>
> > +}
> > +
> > +static void mtk_intx_unmask(struct irq_data *data)
> > +{
> > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > + u32 val;
> > +
> > + val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
> > + val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
> > + writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
>
> Same thing here.
>
> > +}
> > +
> > +/**
> > + * mtk_intx_eoi
> > + * @data: pointer to chip specific data
> > + *
> > + * As an emulated level IRQ, its interrupt status will remain
> > + * until the corresponding de-assert message is received; hence that
> > + * the status can only be cleared when the interrupt has been
> > serviced.
> > + */
> > +static void mtk_intx_eoi(struct irq_data *data)
> > +{
> > + struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > + unsigned long hwirq;
> > +
> > + hwirq = data->hwirq + PCIE_INTX_SHIFT;
> > + writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
> > +}
> > +
> > +static struct irq_chip mtk_intx_irq_chip = {
> > + .irq_mask = mtk_intx_mask,
> > + .irq_unmask = mtk_intx_unmask,
> > + .irq_eoi= mtk_intx_eoi,
> > + .irq_set_affinity = mtk_pcie_set_affinity,
> > + .name = "PCIe",
>
> nit: "PCIe" is not really descriptive. "INTx" would be a bit better.
>
> > +};
> > +
> > +static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int
> > irq,
> > +irq_hw_number_t hwirq)
> > +{
> > + irq_set_chip_and_handler_name(irq, _intx_irq_chip,
> > + handle_fasteoi_irq, "INTx");
> > + irq_set_chip_data(irq, domain->host_data);
>
> You probably want to set the chip_data *before* wiring
> the handler, as otherwise you could end-up with a NULL
> pointer in any of the callbacks if the interrupt fires
> between the two.
>
> > +
> > + return 0;
> > +}
> > +
> > +static const struct irq_domain_ops intx_domain_ops = {
> > + .map = mtk_pcie_intx_map,
> > +};
> > +
> > +static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port,
> > +struct
Re: [v7,4/7] PCI: mediatek-gen3: Add INTx support
On 2021-01-13 11:39, Jianjun Wang wrote:
Add INTx support for MediaTek Gen3 PCIe controller.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 163
1 file changed, 163 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
b/drivers/pci/controller/pcie-mediatek-gen3.c
index c00ea7c167de..7979a2856c35 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -9,6 +9,9 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
@@ -49,6 +52,12 @@
#define PCIE_LINK_STATUS_REG 0x154
#define PCIE_PORT_LINKUP BIT(8)
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
I guess this '24' is actually PCIE_INTX_SHIFT? In this case,
please write it as
GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
to make it clear that you are dealing with one bit per INTx.
+
+#define PCIE_INT_STATUS_REG0x184
+
#define PCIE_TRANS_TABLE_BASE_REG 0x800
#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
@@ -77,6 +86,8 @@
* @phy: PHY controller block
* @clks: PCIe clocks
* @num_clks: PCIe clocks count for this port
+ * @irq: PCIe controller interrupt number
+ * @intx_domain: legacy INTx IRQ domain
*/
struct mtk_pcie_port {
struct device *dev;
@@ -87,6 +98,9 @@ struct mtk_pcie_port {
struct phy *phy;
struct clk_bulk_data *clks;
int num_clks;
+
+ int irq;
+ struct irq_domain *intx_domain;
};
/**
@@ -266,6 +280,149 @@ static int mtk_pcie_startup_port(struct
mtk_pcie_port *port)
return 0;
}
+static int mtk_pcie_set_affinity(struct irq_data *data,
+const struct cpumask *mask, bool force)
+{
+ return -EINVAL;
+}
+
+static void mtk_intx_mask(struct irq_data *data)
+{
+ struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+ u32 val;
+
+ val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+ val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
+ writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
This is missing some locking. Otherwise, two concurrent mask/unmask
for different interrupts will corrupt each other's state.
+}
+
+static void mtk_intx_unmask(struct irq_data *data)
+{
+ struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+ u32 val;
+
+ val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+ val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
+ writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
Same thing here.
+}
+
+/**
+ * mtk_intx_eoi
+ * @data: pointer to chip specific data
+ *
+ * As an emulated level IRQ, its interrupt status will remain
+ * until the corresponding de-assert message is received; hence that
+ * the status can only be cleared when the interrupt has been
serviced.
+ */
+static void mtk_intx_eoi(struct irq_data *data)
+{
+ struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+ unsigned long hwirq;
+
+ hwirq = data->hwirq + PCIE_INTX_SHIFT;
+ writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
+}
+
+static struct irq_chip mtk_intx_irq_chip = {
+ .irq_mask = mtk_intx_mask,
+ .irq_unmask = mtk_intx_unmask,
+ .irq_eoi= mtk_intx_eoi,
+ .irq_set_affinity = mtk_pcie_set_affinity,
+ .name = "PCIe",
nit: "PCIe" is not really descriptive. "INTx" would be a bit better.
+};
+
+static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int
irq,
+irq_hw_number_t hwirq)
+{
+ irq_set_chip_and_handler_name(irq, _intx_irq_chip,
+ handle_fasteoi_irq, "INTx");
+ irq_set_chip_data(irq, domain->host_data);
You probably want to set the chip_data *before* wiring
the handler, as otherwise you could end-up with a NULL
pointer in any of the callbacks if the interrupt fires
between the two.
+
+ return 0;
+}
+
+static const struct irq_domain_ops intx_domain_ops = {
+ .map = mtk_pcie_intx_map,
+};
+
+static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port,
+struct device_node *node)
+{
+ struct device *dev = port->dev;
+ struct device_node *intc_node;
+
+ /* Setup INTx */
+ intc_node = of_get_child_by_name(node, "interrupt-controller");
+ if (!intc_node) {
+ dev_err(dev, "missing PCIe Intc node\n");
+ return -ENODEV;
+ }
+
+ port->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
+ _domain_ops, port);
+ if (!port->intx_domain) {
+ dev_err(dev, "failed to
[v7,4/7] PCI: mediatek-gen3: Add INTx support
Add INTx support for MediaTek Gen3 PCIe controller.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 163
1 file changed, 163 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
b/drivers/pci/controller/pcie-mediatek-gen3.c
index c00ea7c167de..7979a2856c35 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -9,6 +9,9 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
@@ -49,6 +52,12 @@
#define PCIE_LINK_STATUS_REG 0x154
#define PCIE_PORT_LINKUP BIT(8)
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+
+#define PCIE_INT_STATUS_REG0x184
+
#define PCIE_TRANS_TABLE_BASE_REG 0x800
#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
@@ -77,6 +86,8 @@
* @phy: PHY controller block
* @clks: PCIe clocks
* @num_clks: PCIe clocks count for this port
+ * @irq: PCIe controller interrupt number
+ * @intx_domain: legacy INTx IRQ domain
*/
struct mtk_pcie_port {
struct device *dev;
@@ -87,6 +98,9 @@ struct mtk_pcie_port {
struct phy *phy;
struct clk_bulk_data *clks;
int num_clks;
+
+ int irq;
+ struct irq_domain *intx_domain;
};
/**
@@ -266,6 +280,149 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port
*port)
return 0;
}
+static int mtk_pcie_set_affinity(struct irq_data *data,
+const struct cpumask *mask, bool force)
+{
+ return -EINVAL;
+}
+
+static void mtk_intx_mask(struct irq_data *data)
+{
+ struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+ u32 val;
+
+ val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+ val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
+ writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+}
+
+static void mtk_intx_unmask(struct irq_data *data)
+{
+ struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+ u32 val;
+
+ val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+ val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
+ writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+}
+
+/**
+ * mtk_intx_eoi
+ * @data: pointer to chip specific data
+ *
+ * As an emulated level IRQ, its interrupt status will remain
+ * until the corresponding de-assert message is received; hence that
+ * the status can only be cleared when the interrupt has been serviced.
+ */
+static void mtk_intx_eoi(struct irq_data *data)
+{
+ struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+ unsigned long hwirq;
+
+ hwirq = data->hwirq + PCIE_INTX_SHIFT;
+ writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
+}
+
+static struct irq_chip mtk_intx_irq_chip = {
+ .irq_mask = mtk_intx_mask,
+ .irq_unmask = mtk_intx_unmask,
+ .irq_eoi= mtk_intx_eoi,
+ .irq_set_affinity = mtk_pcie_set_affinity,
+ .name = "PCIe",
+};
+
+static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+irq_hw_number_t hwirq)
+{
+ irq_set_chip_and_handler_name(irq, _intx_irq_chip,
+ handle_fasteoi_irq, "INTx");
+ irq_set_chip_data(irq, domain->host_data);
+
+ return 0;
+}
+
+static const struct irq_domain_ops intx_domain_ops = {
+ .map = mtk_pcie_intx_map,
+};
+
+static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port,
+struct device_node *node)
+{
+ struct device *dev = port->dev;
+ struct device_node *intc_node;
+
+ /* Setup INTx */
+ intc_node = of_get_child_by_name(node, "interrupt-controller");
+ if (!intc_node) {
+ dev_err(dev, "missing PCIe Intc node\n");
+ return -ENODEV;
+ }
+
+ port->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
+ _domain_ops, port);
+ if (!port->intx_domain) {
+ dev_err(dev, "failed to get INTx IRQ domain\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void mtk_pcie_irq_teardown(struct mtk_pcie_port *port)
+{
+ irq_set_chained_handler_and_data(port->irq, NULL, NULL);
+
+ if (port->intx_domain)
+ irq_domain_remove(port->intx_domain);
+
+ irq_dispose_mapping(port->irq);
+}
+
+static void mtk_pcie_irq_handler(struct irq_desc *desc)
+{
+ struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
+ struct irq_chip *irqchip = irq_desc_get_chip(desc);
+ unsigned long status;
+ unsigned int virq;
+ irq_hw_number_t irq_bit = PCIE_INTX_SHIFT;
+
+
