RE: [PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
Hi Michael,
> -Original Message-
> From: Michael Turquette [mailto:mturque...@baylibre.com]
[...]
> Hi Dong,
>
> Quoting A.s. Dong (2018-10-21 06:10:48)
> > For dividers with zero indicating clock is disabled, instead of giving
> > a warning each time like "clkx: Zero divisor and
> > CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce
> enable/disable function for it.
> > e.g.
> > 000b - Clock disabled
> > 001b - Divide by 1
> > 010b - Divide by 2
> > ...
>
> I feel bad to NAK this patch after it's been on the list for so long,
Never mind, I feel better than no response about it. :-)
> but this
> implementation really should belong in your hardware specific clock provider
> driver.
>
Got your point.
> This patch expands clk-divider to also be a gate, which is a non-starter.
> Basic
> clock types were meant to remain basic. I'm already imagining how this
> precedent would cause other submissions: "why should I use composite clock
> when we can just add new clk_ops to the basic clock types!" :-(
>
> Also the implementation becomes cleaner when you don't have to make it
> coexist with clk-divider.c. You can drop the flags and just implement a
> machine
> specific clock type that combines gates and dividers.
Sound good to me. The original purpose to put it in framework is in order to
save possible duplicated codes for a similar SoC as the implementation actually
is HW independent. But I think we could start from putting it in machine code
first.
Thanks for the suggestion.
Will update soon and resend.
Regards
Dong Aisheng
>
> Best regards,
> Mike
>
> >
> > Set rate when the clk is disabled will cache the rate request and only
> > when the clk is enabled will the driver actually program the hardware
> > to have the requested divider value. Similarly, when the clk is
> > disabled we'll write a 0 there, but when the clk is enabled we'll
> > restore whatever rate
> > (divider) was chosen last.
> >
> > It does mean that recalc rate will be sort of odd, because when the
> > clk is off it will return 0, and when the clk is on it will return the
> > right rate.
> > So to make things work, we'll need to return the cached rate in recalc
> > rate when the clk is off and read the hardware when the clk is on.
> >
> > NOTE for the default off divider, the recalc rate will still return 0
> > as there's still no proper preset rate. Enable such divider will give
> > user a reminder error message.
> >
> > Cc: Stephen Boyd
> > Cc: Michael Turquette
> > Cc: Shawn Guo
> > Signed-off-by: Dong Aisheng
> >
> > ---
> > ChangeLog:
> > v3->v4:
> > * no changes
> > v2->v3:
> > * split normal and gate ops
> > * fix the possible racy
> > v1->v2:
> > * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
> > ---
> > drivers/clk/clk-divider.c| 152
> +++
> > include/linux/clk-provider.h | 9 +++
> > 2 files changed, 161 insertions(+)
> >
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index b6234a5..b3566fd 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-divider.c
> > @@ -122,6 +122,9 @@ unsigned long divider_recalc_rate(struct clk_hw
> > *hw, unsigned long parent_rate,
> >
> > div = _get_div(table, val, flags, width);
> > if (!div) {
> > + if (flags & CLK_DIVIDER_ZERO_GATE)
> > + return 0;
> > +
> > WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
> > "%s: Zero divisor and
> CLK_DIVIDER_ALLOW_ZERO not set\n",
> > clk_hw_get_name(hw)); @@ -145,6 +148,34
> @@
> > static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> >divider->flags, divider->width); }
> >
> > +static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
> > + unsigned long
> > +parent_rate) {
> > + struct clk_divider *divider = to_clk_divider(hw);
> > + unsigned long flags = 0;
> > + unsigned int val;
> > +
> > + if (divider->lock)
> > + spin_lock_irqsave(divider->lock, flags);
> > + else
> > + __acquire(divider->lock);
> > +
> > + if (!clk_hw_is_enabled(hw)) {
> > + val = divider->cached_val;
> > + } else {
> > + val = clk_readl(divider->reg) >> divider->shift;
> > + val &= clk_div_mask(divider->width);
> > + }
> > +
> > + if (divider->lock)
> > + spin_unlock_irqrestore(divider->lock, flags);
> > + else
> > + __release(divider->lock);
> > +
> > + return divider_recalc_rate(hw, parent_rate, val, divider->table,
> > + divider->flags, divider->width); }
> > +
> > static bool _is_valid_table_div(const struct clk_div_table *table,
> > unsigned
> int
> > div) { @@
Re: [PATCH RESEND V4 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
Hi Dong,
Quoting A.s. Dong (2018-10-21 06:10:48)
> For dividers with zero indicating clock is disabled, instead of giving a
> warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
> set" in exist code, we'd like to introduce enable/disable function for it.
> e.g.
> 000b - Clock disabled
> 001b - Divide by 1
> 010b - Divide by 2
> ...
I feel bad to NAK this patch after it's been on the list for so long,
but this implementation really should belong in your hardware specific
clock provider driver.
This patch expands clk-divider to also be a gate, which is a
non-starter. Basic clock types were meant to remain basic. I'm already
imagining how this precedent would cause other submissions: "why should
I use composite clock when we can just add new clk_ops to the basic
clock types!" :-(
Also the implementation becomes cleaner when you don't have to make it
coexist with clk-divider.c. You can drop the flags and just implement a
machine specific clock type that combines gates and dividers.
Best regards,
Mike
>
> Set rate when the clk is disabled will cache the rate request and only
> when the clk is enabled will the driver actually program the hardware to
> have the requested divider value. Similarly, when the clk is disabled we'll
> write a 0 there, but when the clk is enabled we'll restore whatever rate
> (divider) was chosen last.
>
> It does mean that recalc rate will be sort of odd, because when the clk is
> off it will return 0, and when the clk is on it will return the right rate.
> So to make things work, we'll need to return the cached rate in recalc rate
> when the clk is off and read the hardware when the clk is on.
>
> NOTE for the default off divider, the recalc rate will still return 0 as
> there's still no proper preset rate. Enable such divider will give user
> a reminder error message.
>
> Cc: Stephen Boyd
> Cc: Michael Turquette
> Cc: Shawn Guo
> Signed-off-by: Dong Aisheng
>
> ---
> ChangeLog:
> v3->v4:
> * no changes
> v2->v3:
> * split normal and gate ops
> * fix the possible racy
> v1->v2:
> * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
> ---
> drivers/clk/clk-divider.c| 152
> +++
> include/linux/clk-provider.h | 9 +++
> 2 files changed, 161 insertions(+)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index b6234a5..b3566fd 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -122,6 +122,9 @@ unsigned long divider_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate,
>
> div = _get_div(table, val, flags, width);
> if (!div) {
> + if (flags & CLK_DIVIDER_ZERO_GATE)
> + return 0;
> +
> WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
> "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
> set\n",
> clk_hw_get_name(hw));
> @@ -145,6 +148,34 @@ static unsigned long clk_divider_recalc_rate(struct
> clk_hw *hw,
>divider->flags, divider->width);
> }
>
> +static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + unsigned long flags = 0;
> + unsigned int val;
> +
> + if (divider->lock)
> + spin_lock_irqsave(divider->lock, flags);
> + else
> + __acquire(divider->lock);
> +
> + if (!clk_hw_is_enabled(hw)) {
> + val = divider->cached_val;
> + } else {
> + val = clk_readl(divider->reg) >> divider->shift;
> + val &= clk_div_mask(divider->width);
> + }
> +
> + if (divider->lock)
> + spin_unlock_irqrestore(divider->lock, flags);
> + else
> + __release(divider->lock);
> +
> + return divider_recalc_rate(hw, parent_rate, val, divider->table,
> + divider->flags, divider->width);
> +}
> +
> static bool _is_valid_table_div(const struct clk_div_table *table,
> unsigned int div)
> {
> @@ -437,6 +468,108 @@ static int clk_divider_set_rate(struct clk_hw *hw,
> unsigned long rate,
> return 0;
> }
>
> +static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + unsigned long flags = 0;
> + int value;
> + u32 val;
> +
> + value = divider_get_val(rate, parent_rate, divider->table,
> + divider->width, divider->flags);
> + if (value < 0)
> + return value;
> +
> + if (divider->lock)
> + spin_lock_irqsave(divider->lock, flags);
> + else
> + __acq
