Re: [PATCH v2] Add DMA engine driver for Freescale MPC85xx processors.

2008-02-07 Thread Timur Tabi

Zhang Wei wrote:
Hi, Dan, 


-Original Message-
From: [EMAIL PROTECTED] 


I do not think all the review comments have been addressed, for
example my earlier comments about GFP_ATOMIC and spin_lock_irqsave
[1].  We have two options to take this forward:



Thanks! Some comments need more study, I'll discuss them with you later.


Zhang and Dan,

What's the status on this patch?  Will it make 2.6.25?

--
Timur Tabi
Linux kernel developer at Freescale
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Re: [PATCH v2] Add DMA engine driver for Freescale MPC85xx processors.

2008-02-07 Thread Timur Tabi

Zhang Wei wrote:
Hi, Dan, 


-Original Message-
From: [EMAIL PROTECTED] 


I do not think all the review comments have been addressed, for
example my earlier comments about GFP_ATOMIC and spin_lock_irqsave
[1].  We have two options to take this forward:



Thanks! Some comments need more study, I'll discuss them with you later.


Zhang and Dan,

What's the status on this patch?  Will it make 2.6.25?

--
Timur Tabi
Linux kernel developer at Freescale
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RE: [PATCH v2] Add DMA engine driver for Freescale MPC85xx processors.

2008-01-22 Thread Zhang Wei
Hi, Dan, 

> -Original Message-
> From: [EMAIL PROTECTED] 
>
> I do not think all the review comments have been addressed, for
> example my earlier comments about GFP_ATOMIC and spin_lock_irqsave
> [1].  We have two options to take this forward:
> 

Thanks! Some comments need more study, I'll discuss them with you later.

> 1/ Continue to carry this in the async-tx tree and get an
> Acked-by/Reviewed-by tag from Kumar.
> 2/ Move this to Kumar's tree, and coordinate our pull requests to have
> the async-tx updates hit first.
> 
> I prefer option 1, but I will defer to Kumar.
> 

I also prefer option 1. How about now?

Cheers!
Wei.
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RE: [PATCH v2] Add DMA engine driver for Freescale MPC85xx processors.

2008-01-22 Thread Zhang Wei
Hi, Dan, 

 -Original Message-
 From: [EMAIL PROTECTED] 

 I do not think all the review comments have been addressed, for
 example my earlier comments about GFP_ATOMIC and spin_lock_irqsave
 [1].  We have two options to take this forward:
 

Thanks! Some comments need more study, I'll discuss them with you later.

 1/ Continue to carry this in the async-tx tree and get an
 Acked-by/Reviewed-by tag from Kumar.
 2/ Move this to Kumar's tree, and coordinate our pull requests to have
 the async-tx updates hit first.
 
 I prefer option 1, but I will defer to Kumar.
 

I also prefer option 1. How about now?

Cheers!
Wei.
--
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Re: [PATCH v2] Add DMA engine driver for Freescale MPC85xx processors.

2008-01-10 Thread Dan Williams
On Jan 10, 2008 3:10 AM, Zhang Wei <[EMAIL PROTECTED]> wrote:
> I think your patch is good. What should I do next?
>
> Cheers!
> Wei.
>

I do not think all the review comments have been addressed, for
example my earlier comments about GFP_ATOMIC and spin_lock_irqsave
[1].  We have two options to take this forward:

1/ Continue to carry this in the async-tx tree and get an
Acked-by/Reviewed-by tag from Kumar.
2/ Move this to Kumar's tree, and coordinate our pull requests to have
the async-tx updates hit first.

I prefer option 1, but I will defer to Kumar.

Thanks,
Dan

[1] http://marc.info/?l=linux-kernel=118936050531240=2
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Re: [PATCH v2] Add DMA engine driver for Freescale MPC85xx processors.

2008-01-10 Thread Dan Williams
On Jan 10, 2008 3:10 AM, Zhang Wei [EMAIL PROTECTED] wrote:
 I think your patch is good. What should I do next?

 Cheers!
 Wei.


I do not think all the review comments have been addressed, for
example my earlier comments about GFP_ATOMIC and spin_lock_irqsave
[1].  We have two options to take this forward:

1/ Continue to carry this in the async-tx tree and get an
Acked-by/Reviewed-by tag from Kumar.
2/ Move this to Kumar's tree, and coordinate our pull requests to have
the async-tx updates hit first.

I prefer option 1, but I will defer to Kumar.

Thanks,
Dan

[1] http://marc.info/?l=linux-kernelm=118936050531240w=2
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Re: [PATCH v2] Add DMA engine driver for Freescale MPC85xx processors.

2008-01-09 Thread Dan Williams
On Tue, 2007-10-30 at 02:25 -0700, Zhang Wei wrote:
> The driver implements DMA engine API for Freescale MPC85xx DMA 
> controller, which could be used by devices in the silicon. 
> The driver supports the Basic mode of Freescale MPC85xx DMA
> controller. 
> The MPC85xx processors supported include MPC8540/60, MPC8555,
> MPC8548, 
> MPC8641 and so on. 
> The MPC83xx(MPC8349, MPC8360) are also supported.
> 
> Signed-off-by: Zhang Wei <[EMAIL PROTECTED]> 
> Signed-off-by: Ebony Zhu <[EMAIL PROTECTED]> 
> --- 

Hello Wei,

Since the fixups were straightforward I went ahead and pulled this patch
out of -mm and rebased it on my async-tx patch queue for 2.6.25.  Could
you double check the result, I have only compile tested it?

git pull git://lost.foo-projects.org/~dwillia2/git/iop md-for-linus

I also came across two more review items:
1/ Is there any issue with getting rid of CONFIG_FSL_DMA_SELFTEST?  It
is always on in iop-adma and ioatdma.

2/ I get the following compile warning:
drivers/dma/fsldma.c:731: warning: 'fsl_dma_callback_test' defined but not used

For reference the changes I made when I rebased are appended below.

Thanks,
Dan

 fsldma.c |   66 +++
 1 file changed, 20 insertions(+), 46 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 899b0c0..902e852 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -302,30 +302,6 @@ static void fsl_chan_toggle_ext_start(struct fsl_dma_chan 
*fsl_chan, int enable)
fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
 }
 
-static void fsl_dma_set_src(dma_addr_t addr,
-   struct dma_async_tx_descriptor *tx, int index)
-{
-   struct fsl_desc_sw *desc_node, *desc = tx_to_fsl_desc(tx);
-   struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
-
-   list_for_each_entry(desc_node, >async_tx.tx_list, node) {
-   set_desc_src(fsl_chan, _node->hw, addr);
-   addr += FSL_DMA_BCR_MAX_CNT;
-   }
-}
-
-static void fsl_dma_set_dest(dma_addr_t addr,
-   struct dma_async_tx_descriptor *tx, int index)
-{
-   struct fsl_desc_sw *desc_node, *desc = tx_to_fsl_desc(tx);
-   struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
-
-   list_for_each_entry(desc_node, >async_tx.tx_list, node) {
-   set_desc_dest(fsl_chan, _node->hw, addr);
-   addr += FSL_DMA_BCR_MAX_CNT;
-   }
-}
-
 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
@@ -368,8 +344,6 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
dma_async_tx_descriptor_init(_sw->async_tx,
_chan->common);
-   desc_sw->async_tx.tx_set_src = fsl_dma_set_src;
-   desc_sw->async_tx.tx_set_dest = fsl_dma_set_dest;
desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
INIT_LIST_HEAD(_sw->async_tx.tx_list);
desc_sw->async_tx.phys = pdesc;
@@ -433,7 +407,8 @@ static void fsl_dma_free_chan_resources(struct dma_chan 
*chan)
 }
 
 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
-   struct dma_chan *chan, size_t len, int int_en)
+   struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
+   size_t len, unsigned long flags)
 {
struct fsl_dma_chan *fsl_chan;
struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
@@ -464,6 +439,8 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
copy = min(len, FSL_DMA_BCR_MAX_CNT);
 
set_desc_cnt(fsl_chan, >hw, copy);
+   set_desc_src(fsl_chan, >hw, dma_src);
+   set_desc_dest(fsl_chan, >hw, dma_dest);
 
if (!first)
first = new;
@@ -475,6 +452,8 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
 
prev = new;
len -= copy;
+   dma_src += copy;
+   dma_dest += copy;
 
/* Insert the link descriptor to the LD ring */
list_add_tail(>node, >async_tx.tx_list);
@@ -758,7 +737,7 @@ static int fsl_dma_self_test(struct fsl_dma_chan *fsl_chan)
 {
struct dma_chan *chan;
int err = 0;
-   dma_addr_t addr;
+   dma_addr_t dma_dest, dma_src;
dma_cookie_t cookie;
u8 *src, *dest;
int i;
@@ -790,13 +769,12 @@ static int fsl_dma_self_test(struct fsl_dma_chan 
*fsl_chan)
}
 
/* TX 1 */
-   tx1 = fsl_dma_prep_memcpy(chan, test_size / 2, 0);
+   dma_src = dma_map_single(fsl_chan->dev, src, test_size / 2,
+DMA_TO_DEVICE);
+   dma_dest = dma_map_single(fsl_chan->dev, dest, test_size / 2,
+ 

Re: [PATCH v2] Add DMA engine driver for Freescale MPC85xx processors.

2008-01-09 Thread Dan Williams
On Tue, 2007-10-30 at 02:25 -0700, Zhang Wei wrote:
 The driver implements DMA engine API for Freescale MPC85xx DMA 
 controller, which could be used by devices in the silicon. 
 The driver supports the Basic mode of Freescale MPC85xx DMA
 controller. 
 The MPC85xx processors supported include MPC8540/60, MPC8555,
 MPC8548, 
 MPC8641 and so on. 
 The MPC83xx(MPC8349, MPC8360) are also supported.
 
 Signed-off-by: Zhang Wei [EMAIL PROTECTED] 
 Signed-off-by: Ebony Zhu [EMAIL PROTECTED] 
 --- 

Hello Wei,

Since the fixups were straightforward I went ahead and pulled this patch
out of -mm and rebased it on my async-tx patch queue for 2.6.25.  Could
you double check the result, I have only compile tested it?

git pull git://lost.foo-projects.org/~dwillia2/git/iop md-for-linus

I also came across two more review items:
1/ Is there any issue with getting rid of CONFIG_FSL_DMA_SELFTEST?  It
is always on in iop-adma and ioatdma.

2/ I get the following compile warning:
drivers/dma/fsldma.c:731: warning: 'fsl_dma_callback_test' defined but not used

For reference the changes I made when I rebased are appended below.

Thanks,
Dan

 fsldma.c |   66 +++
 1 file changed, 20 insertions(+), 46 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 899b0c0..902e852 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -302,30 +302,6 @@ static void fsl_chan_toggle_ext_start(struct fsl_dma_chan 
*fsl_chan, int enable)
fsl_chan-feature = ~FSL_DMA_CHAN_START_EXT;
 }
 
-static void fsl_dma_set_src(dma_addr_t addr,
-   struct dma_async_tx_descriptor *tx, int index)
-{
-   struct fsl_desc_sw *desc_node, *desc = tx_to_fsl_desc(tx);
-   struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx-chan);
-
-   list_for_each_entry(desc_node, desc-async_tx.tx_list, node) {
-   set_desc_src(fsl_chan, desc_node-hw, addr);
-   addr += FSL_DMA_BCR_MAX_CNT;
-   }
-}
-
-static void fsl_dma_set_dest(dma_addr_t addr,
-   struct dma_async_tx_descriptor *tx, int index)
-{
-   struct fsl_desc_sw *desc_node, *desc = tx_to_fsl_desc(tx);
-   struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx-chan);
-
-   list_for_each_entry(desc_node, desc-async_tx.tx_list, node) {
-   set_desc_dest(fsl_chan, desc_node-hw, addr);
-   addr += FSL_DMA_BCR_MAX_CNT;
-   }
-}
-
 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
@@ -368,8 +344,6 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
dma_async_tx_descriptor_init(desc_sw-async_tx,
fsl_chan-common);
-   desc_sw-async_tx.tx_set_src = fsl_dma_set_src;
-   desc_sw-async_tx.tx_set_dest = fsl_dma_set_dest;
desc_sw-async_tx.tx_submit = fsl_dma_tx_submit;
INIT_LIST_HEAD(desc_sw-async_tx.tx_list);
desc_sw-async_tx.phys = pdesc;
@@ -433,7 +407,8 @@ static void fsl_dma_free_chan_resources(struct dma_chan 
*chan)
 }
 
 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
-   struct dma_chan *chan, size_t len, int int_en)
+   struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
+   size_t len, unsigned long flags)
 {
struct fsl_dma_chan *fsl_chan;
struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
@@ -464,6 +439,8 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
copy = min(len, FSL_DMA_BCR_MAX_CNT);
 
set_desc_cnt(fsl_chan, new-hw, copy);
+   set_desc_src(fsl_chan, new-hw, dma_src);
+   set_desc_dest(fsl_chan, new-hw, dma_dest);
 
if (!first)
first = new;
@@ -475,6 +452,8 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
 
prev = new;
len -= copy;
+   dma_src += copy;
+   dma_dest += copy;
 
/* Insert the link descriptor to the LD ring */
list_add_tail(new-node, first-async_tx.tx_list);
@@ -758,7 +737,7 @@ static int fsl_dma_self_test(struct fsl_dma_chan *fsl_chan)
 {
struct dma_chan *chan;
int err = 0;
-   dma_addr_t addr;
+   dma_addr_t dma_dest, dma_src;
dma_cookie_t cookie;
u8 *src, *dest;
int i;
@@ -790,13 +769,12 @@ static int fsl_dma_self_test(struct fsl_dma_chan 
*fsl_chan)
}
 
/* TX 1 */
-   tx1 = fsl_dma_prep_memcpy(chan, test_size / 2, 0);
+   dma_src = dma_map_single(fsl_chan-dev, src, test_size / 2,
+DMA_TO_DEVICE);
+   dma_dest = dma_map_single(fsl_chan-dev, dest, test_size / 2,
+