Re: [PATCH v6 1/1] mfd: da9063: Support SMBus and I2C mode
On Wed, 17 Mar 2021, Jonas Mark (BT-FIR/ENG1-Grb) wrote: > Hi, > > > > From: Hubert Streidl > > > > > > By default the PMIC DA9063 2-wire interface is SMBus compliant. This > > > means the PMIC will automatically reset the interface when the clock > > > signal ceases for more than the SMBus timeout of 35 ms. > > > > > > If the I2C driver / device is not capable of creating atomic I2C > > > transactions, a context change can cause a ceasing of the clock signal. > > > This can happen if for example a real-time thread is scheduled. Then > > > the DA9063 in SMBus mode will reset the 2-wire interface. Subsequently > > > a write message could end up in the wrong register. This could cause > > > unpredictable system behavior. > > > > > > The DA9063 PMIC also supports an I2C compliant mode for the 2-wire > > > interface. This mode does not reset the interface when the clock > > > signal ceases. Thus the problem depicted above does not occur. > > > > > > This patch tests for the bus functionality "I2C_FUNC_I2C". It can > > > reasonably be assumed that the bus cannot obey SMBus timings if this > > > functionality is set. SMBus commands most probably are emulated in > > > this case which is prone to the latency issue described above. > > > > > > This patch enables the I2C bus mode if I2C_FUNC_I2C is set or > > > otherwise keeps the default SMBus mode. > > > > > > Signed-off-by: Hubert Streidl > > > Signed-off-by: Mark Jonas > > > > Applied with Wolfram's RB, thanks. > > Thank you very much for your support to all reviewers. Any time. -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
RE: [PATCH v6 1/1] mfd: da9063: Support SMBus and I2C mode
On 16 March 2021 16:23, Mark Jonas wrote: > From: Hubert Streidl > > By default the PMIC DA9063 2-wire interface is SMBus compliant. This > means the PMIC will automatically reset the interface when the clock > signal ceases for more than the SMBus timeout of 35 ms. > > If the I2C driver / device is not capable of creating atomic I2C > transactions, a context change can cause a ceasing of the clock signal. > This can happen if for example a real-time thread is scheduled. Then > the DA9063 in SMBus mode will reset the 2-wire interface. Subsequently > a write message could end up in the wrong register. This could cause > unpredictable system behavior. > > The DA9063 PMIC also supports an I2C compliant mode for the 2-wire > interface. This mode does not reset the interface when the clock > signal ceases. Thus the problem depicted above does not occur. > > This patch tests for the bus functionality "I2C_FUNC_I2C". It can > reasonably be assumed that the bus cannot obey SMBus timings if > this functionality is set. SMBus commands most probably are emulated > in this case which is prone to the latency issue described above. > > This patch enables the I2C bus mode if I2C_FUNC_I2C is set or > otherwise keeps the default SMBus mode. > > Signed-off-by: Hubert Streidl > Signed-off-by: Mark Jonas Thanks for your efforts on this Mark.
Re: [PATCH v6 1/1] mfd: da9063: Support SMBus and I2C mode
On Tue, 16 Mar 2021, Mark Jonas wrote: > From: Hubert Streidl > > By default the PMIC DA9063 2-wire interface is SMBus compliant. This > means the PMIC will automatically reset the interface when the clock > signal ceases for more than the SMBus timeout of 35 ms. > > If the I2C driver / device is not capable of creating atomic I2C > transactions, a context change can cause a ceasing of the clock signal. > This can happen if for example a real-time thread is scheduled. Then > the DA9063 in SMBus mode will reset the 2-wire interface. Subsequently > a write message could end up in the wrong register. This could cause > unpredictable system behavior. > > The DA9063 PMIC also supports an I2C compliant mode for the 2-wire > interface. This mode does not reset the interface when the clock > signal ceases. Thus the problem depicted above does not occur. > > This patch tests for the bus functionality "I2C_FUNC_I2C". It can > reasonably be assumed that the bus cannot obey SMBus timings if > this functionality is set. SMBus commands most probably are emulated > in this case which is prone to the latency issue described above. > > This patch enables the I2C bus mode if I2C_FUNC_I2C is set or > otherwise keeps the default SMBus mode. > > Signed-off-by: Hubert Streidl > Signed-off-by: Mark Jonas > --- > Changes in v6: > - Fixed checkpatch check 'unaligned broken line'. > > Changes in v5: > - Restructured according to feedback by Lee Jones. > > Changes in v4: > - Remove logging of selected 2-wire bus mode. > > Changes in v3: > - busmode now contains the correct bit DA9063_TWOWIRE_TO > > Changes in v2: > - Implement proposal by Adam Thomson and Wolfram Sang to check for > functionality I2C_FUNC_I2C instead of introducing a new DT property. > > drivers/mfd/da9063-i2c.c | 10 ++ > include/linux/mfd/da9063/registers.h | 3 +++ > 2 files changed, 13 insertions(+) Applied with Wolfram's RB, thanks. -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
Re: [PATCH v6 1/1] mfd: da9063: Support SMBus and I2C mode
On Tue, Mar 16, 2021 at 05:22:37PM +0100, Mark Jonas wrote: > From: Hubert Streidl > > By default the PMIC DA9063 2-wire interface is SMBus compliant. This > means the PMIC will automatically reset the interface when the clock > signal ceases for more than the SMBus timeout of 35 ms. > > If the I2C driver / device is not capable of creating atomic I2C > transactions, a context change can cause a ceasing of the clock signal. > This can happen if for example a real-time thread is scheduled. Then > the DA9063 in SMBus mode will reset the 2-wire interface. Subsequently > a write message could end up in the wrong register. This could cause > unpredictable system behavior. > > The DA9063 PMIC also supports an I2C compliant mode for the 2-wire > interface. This mode does not reset the interface when the clock > signal ceases. Thus the problem depicted above does not occur. > > This patch tests for the bus functionality "I2C_FUNC_I2C". It can > reasonably be assumed that the bus cannot obey SMBus timings if > this functionality is set. SMBus commands most probably are emulated > in this case which is prone to the latency issue described above. > > This patch enables the I2C bus mode if I2C_FUNC_I2C is set or > otherwise keeps the default SMBus mode. > > Signed-off-by: Hubert Streidl > Signed-off-by: Mark Jonas Reviewed-by: Wolfram Sang signature.asc Description: PGP signature