RE: [RFC] spi-nor: fix cross die reads on Micron multi-die devices
> Hi Bean, > > On Thu, 21 Jan 2016 01:06:48 + > Bean Huo 霍斌斌 (beanhuo) wrote: > > > Hi, Adam and Boris > > > > For Micron MT25Q ,MT25T and MT35Q, they does not exist this action > > even they are Multi-die devices. So when the last byte of the die > > selected is read, the next byte output is the first byte of next die(not the > same die). > > You can check this by extended address register chapter in our > > datasheet, there are detail Information. > > I never said you were wrong ;), I just asked if it was relevant to > differentiate > the two cases. IOW, would the implementation proposed by Adam work > correctly on all chips? And what is the real performance penalty for > MT25Q ,MT25T and MT35Q if we decide to split the read command in several > reads to handle this cross die case? For this , performance penalty is tiny, can ignore. SPI NOR read performance only depends on SPI I/O clock. Not the same as NAND. > Best Regards, > > Boris > > -- > Boris Brezillon, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com
Re: [RFC] spi-nor: fix cross die reads on Micron multi-die devices
Hi Bean, On Thu, 21 Jan 2016 01:06:48 + Bean Huo 霍斌斌 (beanhuo) wrote: > Hi, Adam and Boris > > For Micron MT25Q ,MT25T and MT35Q, they does not exist this action even they > are > Multi-die devices. So when the last byte of the die selected is read, the > next byte output > is the first byte of next die(not the same die). > You can check this by extended address register chapter in our datasheet, > there are detail > Information. I never said you were wrong ;), I just asked if it was relevant to differentiate the two cases. IOW, would the implementation proposed by Adam work correctly on all chips? And what is the real performance penalty for MT25Q ,MT25T and MT35Q if we decide to split the read command in several reads to handle this cross die case? Best Regards, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
RE: [RFC] spi-nor: fix cross die reads on Micron multi-die devices
Hi, Adam and Boris For Micron MT25Q ,MT25T and MT35Q, they does not exist this action even they are Multi-die devices. So when the last byte of the die selected is read, the next byte output is the first byte of next die(not the same die). You can check this by extended address register chapter in our datasheet, there are detail Information. > Hi, > > Thanks for looking at the this. > > I can rewrite so it only affects N25Q devices, I hoped a simpler > implementation would outweigh the small overhead incurred on non affected > devices. > > Do you know if there are any plans for MT25* based multi-die devices and if > they would have the same issue? > > Thanks, > > Adam > > On Wed, Jan 20, 2016 at 2:45 AM, Bean Huo 霍斌斌 (beanhuo) > wrote: > > Hi, Adam > > This is true, but this only exist in Micron 65nm spi nor N25Q. > > For our 45nm spi nor MT25Q , MT25TL and MT25Q, does exist this > question. > > So I think, can you differentiate between these in your patch? > > > >> From: Adam Somerville > >> > >> So as far as I can see there is a bug in the spi-nor driver when > >> issuing die boundary crossing reads on Micron multi-die devices. > >> Micron N25Q512A, N25Q00AA and probably any other Micron multi-die > >> devices do not support a single read request that crosses a die boundary. > >> > >> The current behaviour is that the address on the device wraps back to > >> the start of the first die, with any data returned beyond the > >> boundary being from the start of the first die. > >>
