Re: [PATCH] clk: fractional-divider: prevent division by zero

[Heikki Krogerus]

On Fri, Jan 16, 2015 at 02:29:13PM -0800, Stephen Boyd wrote:
> On 01/16/2015 04:37 AM, Heikki Krogerus wrote:
> > Preventing division by zero condition by making sure that
> > the initial n and m values are not 0.
> >
> > Signed-off-by: Heikki Krogerus 
> > ---
> >  drivers/clk/clk-fractional-divider.c | 9 +
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/clk/clk-fractional-divider.c 
> > b/drivers/clk/clk-fractional-divider.c
> > index 82a59d0..dc91da7 100644
> > --- a/drivers/clk/clk-fractional-divider.c
> > +++ b/drivers/clk/clk-fractional-divider.c
> > @@ -104,6 +104,7 @@ struct clk *clk_register_fractional_divider(struct 
> > device *dev,
> > struct clk_fractional_divider *fd;
> > struct clk_init_data init;
> > struct clk *clk;
> > +   u32 val;
> >  
> > fd = kzalloc(sizeof(*fd), GFP_KERNEL);
> > if (!fd) {
> > @@ -126,6 +127,14 @@ struct clk *clk_register_fractional_divider(struct 
> > device *dev,
> > fd->lock = lock;
> > fd->hw.init = &init;
> >  
> > +   /* Prevent division by zero */
> > +   val = clk_readl(fd->reg);
> > +   if (!(val & fd->nmask))
> > +   val |= 1 << fd->nshift;
> > +   if (!(val & fd->mmask))
> > +   val |= 1 << fd->mshift;
> > +   clk_writel(val, fd->reg);
> > +
> > clk = clk_register(dev, &fd->hw);
> > if (IS_ERR(clk))
> > kfree(fd);
> 
> Sorry I don't understand this at all. Does your hardware support a value
> of 0 in the register? Doesn't that mean "bypass" so that the rate of the
> parent bypasses the divider? If so, why aren't we fixing the
> recalc_rate() logic to check for a special case of 0?

OK. Makes sense.

-- 
heikki
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Re: [PATCH] clk: fractional-divider: prevent division by zero

[Stephen Boyd]

On 01/16/2015 04:37 AM, Heikki Krogerus wrote:
> Preventing division by zero condition by making sure that
> the initial n and m values are not 0.
>
> Signed-off-by: Heikki Krogerus 
> ---
>  drivers/clk/clk-fractional-divider.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/clk/clk-fractional-divider.c 
> b/drivers/clk/clk-fractional-divider.c
> index 82a59d0..dc91da7 100644
> --- a/drivers/clk/clk-fractional-divider.c
> +++ b/drivers/clk/clk-fractional-divider.c
> @@ -104,6 +104,7 @@ struct clk *clk_register_fractional_divider(struct device 
> *dev,
>   struct clk_fractional_divider *fd;
>   struct clk_init_data init;
>   struct clk *clk;
> + u32 val;
>  
>   fd = kzalloc(sizeof(*fd), GFP_KERNEL);
>   if (!fd) {
> @@ -126,6 +127,14 @@ struct clk *clk_register_fractional_divider(struct 
> device *dev,
>   fd->lock = lock;
>   fd->hw.init = &init;
>  
> + /* Prevent division by zero */
> + val = clk_readl(fd->reg);
> + if (!(val & fd->nmask))
> + val |= 1 << fd->nshift;
> + if (!(val & fd->mmask))
> + val |= 1 << fd->mshift;
> + clk_writel(val, fd->reg);
> +
>   clk = clk_register(dev, &fd->hw);
>   if (IS_ERR(clk))
>   kfree(fd);

Sorry I don't understand this at all. Does your hardware support a value
of 0 in the register? Doesn't that mean "bypass" so that the rate of the
parent bypasses the divider? If so, why aren't we fixing the
recalc_rate() logic to check for a special case of 0?

-- 
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a Linux Foundation Collaborative Project

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