Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Thu, 2015-08-20 at 22:02 +0200, Thomas Gleixner wrote: > On Thu, 20 Aug 2015, Tim Chen wrote: > > From: Tim Chen > > Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions > > implementations > >sha: is not a proper subsystem name > >x86/cpufeatures: is the correct one > > > Enable cpuid check for Intel SHA extensions implementations > > This patch does not enable any checks. It merily adds the feature bit. > > > The Intel Secure Hash Algorithm Extensions are designed to improve the > > performance > > of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. > > Again there is no check. > > > This will allow the feature to be shown in the /proc/cpuinfo. > > > > The SHA extension programming guide is found in chapter 8 of the Intel > > Architecture Instruction Set Extensions Programming reference: > > https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf > > > > Originally-by: Chandramouli Narayanan > > So Mouli left the company. What's the point of having his Intel mail > address here and in the Cc list? Thomas, Thanks for your input. Hopefully the attached patch below addresses issues you've raised. Mouli was copied on his new email address too. Tim --->8--- From: Tim Chen Subject: [PATCH] x86/cpufeatures: Enable cpuid for Intel SHA extensions Add Intel CPUID for Intel Secure Hash Algorithm Extensions. This feature provides new instructions for accelerated computation of SHA-1 and SHA-256. This allows the feature to be shown in the /proc/cpuinfo for cpus that support it. Refer to SHA extension programming guide in chapter 8.2 of the Intel Architecture Instruction Set Extensions Programming reference for definition of this feature's cpuid: CPUID.(EAX=07H, ECX=0):EBX.SHA [bit 29] = 1 https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan Signed-off-by: Tim Chen --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Thu, 2015-08-20 at 22:02 +0200, Thomas Gleixner wrote: On Thu, 20 Aug 2015, Tim Chen wrote: From: Tim Chen tim.c.c...@linux.intel.com Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations sha: is not a proper subsystem name x86/cpufeatures: is the correct one Enable cpuid check for Intel SHA extensions implementations This patch does not enable any checks. It merily adds the feature bit. The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. Again there is no check. This will allow the feature to be shown in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan mo...@linux.intel.com So Mouli left the company. What's the point of having his Intel mail address here and in the Cc list? Thomas, Thanks for your input. Hopefully the attached patch below addresses issues you've raised. Mouli was copied on his new email address too. Tim ---8--- From: Tim Chen tim.c.c...@linux.intel.com Subject: [PATCH] x86/cpufeatures: Enable cpuid for Intel SHA extensions Add Intel CPUID for Intel Secure Hash Algorithm Extensions. This feature provides new instructions for accelerated computation of SHA-1 and SHA-256. This allows the feature to be shown in the /proc/cpuinfo for cpus that support it. Refer to SHA extension programming guide in chapter 8.2 of the Intel Architecture Instruction Set Extensions Programming reference for definition of this feature's cpuid: CPUID.(EAX=07H, ECX=0):EBX.SHA [bit 29] = 1 https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan mouli_7...@yahoo.com Signed-off-by: Tim Chen tim.c.c...@linux.intel.com --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Thu, 20 Aug 2015, Tim Chen wrote: > From: Tim Chen > Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions > implementations sha: is not a proper subsystem name x86/cpufeatures: is the correct one > Enable cpuid check for Intel SHA extensions implementations This patch does not enable any checks. It merily adds the feature bit. > The Intel Secure Hash Algorithm Extensions are designed to improve the > performance > of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. Again there is no check. > This will allow the feature to be shown in the /proc/cpuinfo. > > The SHA extension programming guide is found in chapter 8 of the Intel > Architecture Instruction Set Extensions Programming reference: > https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf > > Originally-by: Chandramouli Narayanan So Mouli left the company. What's the point of having his Intel mail address here and in the Cc list? Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Thu, 2015-08-20 at 06:08 +0200, Borislav Petkov wrote: > On Wed, Aug 19, 2015 at 09:49:58AM -0700, Tim Chen wrote: > > Mouli did the patch originally but he left the company. So > > I'm picking it up. > > So the SOB chain should be: > > From: you > > > > Originally-by: Mouli > Signed-off-by: you > Thanks. Revised patch embedded below. Tim --->8--- From: Tim Chen Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. This will allow the feature to be shown in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan Signed-off-by: Tim Chen --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Thu, 2015-08-20 at 06:08 +0200, Borislav Petkov wrote: On Wed, Aug 19, 2015 at 09:49:58AM -0700, Tim Chen wrote: Mouli did the patch originally but he left the company. So I'm picking it up. So the SOB chain should be: From: you commit message Originally-by: Mouli Signed-off-by: you Thanks. Revised patch embedded below. Tim ---8--- From: Tim Chen tim.c.c...@linux.intel.com Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. This will allow the feature to be shown in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan mo...@linux.intel.com Signed-off-by: Tim Chen tim.c.c...@linux.intel.com --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Thu, 20 Aug 2015, Tim Chen wrote: From: Tim Chen tim.c.c...@linux.intel.com Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations sha: is not a proper subsystem name x86/cpufeatures: is the correct one Enable cpuid check for Intel SHA extensions implementations This patch does not enable any checks. It merily adds the feature bit. The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. Again there is no check. This will allow the feature to be shown in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Originally-by: Chandramouli Narayanan mo...@linux.intel.com So Mouli left the company. What's the point of having his Intel mail address here and in the Cc list? Thanks, tglx -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Wed, Aug 19, 2015 at 09:49:58AM -0700, Tim Chen wrote: > On Tue, 2015-08-18 at 18:46 +0200, Thomas Gleixner wrote: > > On Mon, 17 Aug 2015, Tim Chen wrote: > > > Signed-off-by: Chandramouli Narayanan > > > Signed-off-by: Tim Chen > > > > And now the question who authored this complex one liner > > > > Mouli did the patch originally but he left the company. So > I'm picking it up. So the SOB chain should be: From: you Originally-by: Mouli Signed-off-by: you -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) -- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Tue, 2015-08-18 at 18:46 +0200, Thomas Gleixner wrote: > On Mon, 17 Aug 2015, Tim Chen wrote: > > Signed-off-by: Chandramouli Narayanan > > Signed-off-by: Tim Chen > > And now the question who authored this complex one liner > Mouli did the patch originally but he left the company. So I'm picking it up. Tim > > --- > > arch/x86/include/asm/cpufeature.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/x86/include/asm/cpufeature.h > > b/arch/x86/include/asm/cpufeature.h > > index 3d6606f..a94f83d 100644 > > --- a/arch/x86/include/asm/cpufeature.h > > +++ b/arch/x86/include/asm/cpufeature.h > > @@ -239,6 +239,7 @@ > > #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ > > #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and > > Reciprocal */ > > #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict > > Detection */ > > +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction > > Extensions */ > > > > /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ > > #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ > > -- > > 1.8.3.1 > > > > > > > > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Tue, 2015-08-18 at 18:46 +0200, Thomas Gleixner wrote: On Mon, 17 Aug 2015, Tim Chen wrote: Signed-off-by: Chandramouli Narayanan mo...@linux.intel.com Signed-off-by: Tim Chen tim.c.c...@linux.intel.com And now the question who authored this complex one liner Mouli did the patch originally but he left the company. So I'm picking it up. Tim --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Wed, Aug 19, 2015 at 09:49:58AM -0700, Tim Chen wrote: On Tue, 2015-08-18 at 18:46 +0200, Thomas Gleixner wrote: On Mon, 17 Aug 2015, Tim Chen wrote: Signed-off-by: Chandramouli Narayanan mo...@linux.intel.com Signed-off-by: Tim Chen tim.c.c...@linux.intel.com And now the question who authored this complex one liner Mouli did the patch originally but he left the company. So I'm picking it up. So the SOB chain should be: From: you commit message Originally-by: Mouli Signed-off-by: you -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) -- -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Mon, 17 Aug 2015, Tim Chen wrote: > Signed-off-by: Chandramouli Narayanan > Signed-off-by: Tim Chen And now the question who authored this complex one liner > --- > arch/x86/include/asm/cpufeature.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeature.h > b/arch/x86/include/asm/cpufeature.h > index 3d6606f..a94f83d 100644 > --- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -239,6 +239,7 @@ > #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ > #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and > Reciprocal */ > #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ > +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction > Extensions */ > > /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ > #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ > -- > 1.8.3.1 > > > > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Mon, 17 Aug 2015, Tim Chen wrote: Signed-off-by: Chandramouli Narayanan mo...@linux.intel.com Signed-off-by: Tim Chen tim.c.c...@linux.intel.com And now the question who authored this complex one liner --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Mon, 2015-08-17 at 14:19 -0700, Dave Hansen wrote: > On 08/17/2015 01:44 PM, Tim Chen wrote: > > @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; > > #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) > > #define cpu_has_topoextboot_cpu_has(X86_FEATURE_TOPOEXT) > > #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) > > +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI) > > I think we're trying not to add these cpu_has_* macros any more. For > MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly. > > In the patch description, it might also be nice to remind folks that > this will feature will also show up as "sha_ni" in /proc/cpuinfo. Okay, in that case, I've modified the patch to below: Tim --->8--- Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations To: Thomas Gleixner , Ingo Molnar , H. Peter Anvin Cc: Herbert Xu , Chandramouli Narayanan , x...@kernel.org, linux-kernel@vger.kernel.org The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. This will allow the feature to be shown as sha_ni in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Signed-off-by: Chandramouli Narayanan Signed-off-by: Tim Chen --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On 08/17/2015 01:44 PM, Tim Chen wrote: > @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; > #define cpu_has_eager_fpuboot_cpu_has(X86_FEATURE_EAGER_FPU) > #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) > #define cpu_has_bpextboot_cpu_has(X86_FEATURE_BPEXT) > +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI) I think we're trying not to add these cpu_has_* macros any more. For MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly. In the patch description, it might also be nice to remind folks that this will feature will also show up as "sha_ni" in /proc/cpuinfo. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On Mon, 2015-08-17 at 14:19 -0700, Dave Hansen wrote: On 08/17/2015 01:44 PM, Tim Chen wrote: @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) #define cpu_has_topoextboot_cpu_has(X86_FEATURE_TOPOEXT) #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI) I think we're trying not to add these cpu_has_* macros any more. For MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly. In the patch description, it might also be nice to remind folks that this will feature will also show up as sha_ni in /proc/cpuinfo. Okay, in that case, I've modified the patch to below: Tim ---8--- Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations To: Thomas Gleixner t...@linutronix.de, Ingo Molnar mi...@redhat.com, H. Peter Anvin h...@zytor.com Cc: Herbert Xu herb...@gondor.apana.org.au, Chandramouli Narayanan mo...@linux.intel.com, x...@kernel.org, linux-kernel@vger.kernel.org The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. This will allow the feature to be shown as sha_ni in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Signed-off-by: Chandramouli Narayanan mo...@linux.intel.com Signed-off-by: Tim Chen tim.c.c...@linux.intel.com --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations
On 08/17/2015 01:44 PM, Tim Chen wrote: @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; #define cpu_has_eager_fpuboot_cpu_has(X86_FEATURE_EAGER_FPU) #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) #define cpu_has_bpextboot_cpu_has(X86_FEATURE_BPEXT) +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI) I think we're trying not to add these cpu_has_* macros any more. For MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly. In the patch description, it might also be nice to remind folks that this will feature will also show up as sha_ni in /proc/cpuinfo. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
