Re: [PATCH] x86/cpu: Add new Airmont variant to Intel family
Hi Peter,
On 23/8/2019 5:03 PM, Peter Zijlstra wrote:
On Thu, Aug 22, 2019 at 01:35:44PM -0700, Luck, Tony wrote:
From: Tony Luck
One of the use cases for this processor is as a network
processor. So give it an "_NP" tag for now. Could be changed
later if it turns out to group with some other tag.
Signed-off-by: Tony Luck
---
arch/x86/include/asm/intel-family.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/intel-family.h
b/arch/x86/include/asm/intel-family.h
index 5c05b2d389c3..23ed388a3a56 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -95,6 +95,7 @@
#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
+#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
#define INTEL_FAM6_ATOM_GOLDMONT_D0x5F /* Denverton */
Since it is 'just another airmont' with bits on, should we not then also
add it to all ATOM_AIRMONT sites already present in the kernel?
something like the below; except there were a few sites I skipped
because 'no clue'.
Also, while going over that, it looked like we missed AIRMONT_MID from a
few sites.
I'm thinking we want to add as many of these sites as possible and
correct when adding a new define; esp. for older microarchs that are
already well supported.
[PATCH v2 3/3] that i had sent with this series adds these changes which
are applicable to _NP. Please see below link:
https://lkml.org/lkml/2019/8/16/170
Above patch might have missed few additional points which still apply.
Regards,
Rahul
---
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 648260b5f367..56e6875b6882 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4647,6 +4647,7 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_ATOM_SILVERMONT_MID:
case INTEL_FAM6_ATOM_AIRMONT:
case INTEL_FAM6_ATOM_AIRMONT_MID:
+ case INTEL_FAM6_ATOM_AIRMONT_NP:
memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 688592b34564..1e999092de22 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -602,6 +602,7 @@ static const struct x86_cpu_id intel_cstates_match[]
__initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT, slm_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_X, slm_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT, slm_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT_NP, slm_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE, snb_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 9431447541e9..fe2323f114c0 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -72,6 +72,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ATOM_SILVERMONT:
case INTEL_FAM6_ATOM_SILVERMONT_X:
case INTEL_FAM6_ATOM_AIRMONT:
+ case INTEL_FAM6_ATOM_AIRMONT_NP:
case INTEL_FAM6_ATOM_GOLDMONT:
case INTEL_FAM6_ATOM_GOLDMONT_X:
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5cc2d51cc25e..a3ccee6a16a5 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1053,6 +1053,7 @@ static const __initconst struct x86_cpu_id
cpu_vuln_whitelist[] = {
VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
+ VULNWL_INTEL(ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 067858fe4db8..bde7a0c8fa8b 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -64,6 +64,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
INTEL_CPU_FAM6(ATOM_SILVERMONT, freq_desc_byt),
INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
INTEL_CPU_FAM6(ATOM_AIRMONT,freq_desc_cht),
+ INTEL_CPU_FAM6(ATOM_AIRMONT_NP, freq_desc_cht),
INTEL_CPU_FAM6(ATOM_AIRMONT_MID,freq_desc_ann),
{}
};
diff --git a/arch/x86/platform/atom/punit_atom_debug.c
b/arch/x86/platform/atom/punit_atom_debug.c
index ee6b0780bea1..52990f68af70
Re: [PATCH] x86/cpu: Add new Airmont variant to Intel family
On Thu, Aug 22, 2019 at 01:35:44PM -0700, Luck, Tony wrote:
> From: Tony Luck
>
> One of the use cases for this processor is as a network
> processor. So give it an "_NP" tag for now. Could be changed
> later if it turns out to group with some other tag.
>
> Signed-off-by: Tony Luck
> ---
> arch/x86/include/asm/intel-family.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/intel-family.h
> b/arch/x86/include/asm/intel-family.h
> index 5c05b2d389c3..23ed388a3a56 100644
> --- a/arch/x86/include/asm/intel-family.h
> +++ b/arch/x86/include/asm/intel-family.h
> @@ -95,6 +95,7 @@
>
> #define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell
> */
> #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
> +#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
>
> #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
> #define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
Since it is 'just another airmont' with bits on, should we not then also
add it to all ATOM_AIRMONT sites already present in the kernel?
something like the below; except there were a few sites I skipped
because 'no clue'.
Also, while going over that, it looked like we missed AIRMONT_MID from a
few sites.
I'm thinking we want to add as many of these sites as possible and
correct when adding a new define; esp. for older microarchs that are
already well supported.
---
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 648260b5f367..56e6875b6882 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4647,6 +4647,7 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_ATOM_SILVERMONT_MID:
case INTEL_FAM6_ATOM_AIRMONT:
case INTEL_FAM6_ATOM_AIRMONT_MID:
+ case INTEL_FAM6_ATOM_AIRMONT_NP:
memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 688592b34564..1e999092de22 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -602,6 +602,7 @@ static const struct x86_cpu_id intel_cstates_match[]
__initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT, slm_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT_X, slm_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT, slm_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT_NP, slm_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE, snb_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 9431447541e9..fe2323f114c0 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -72,6 +72,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ATOM_SILVERMONT:
case INTEL_FAM6_ATOM_SILVERMONT_X:
case INTEL_FAM6_ATOM_AIRMONT:
+ case INTEL_FAM6_ATOM_AIRMONT_NP:
case INTEL_FAM6_ATOM_GOLDMONT:
case INTEL_FAM6_ATOM_GOLDMONT_X:
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5cc2d51cc25e..a3ccee6a16a5 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1053,6 +1053,7 @@ static const __initconst struct x86_cpu_id
cpu_vuln_whitelist[] = {
VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
+ VULNWL_INTEL(ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY |
NO_SWAPGS),
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 067858fe4db8..bde7a0c8fa8b 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -64,6 +64,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
INTEL_CPU_FAM6(ATOM_SILVERMONT, freq_desc_byt),
INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
INTEL_CPU_FAM6(ATOM_AIRMONT,freq_desc_cht),
+ INTEL_CPU_FAM6(ATOM_AIRMONT_NP, freq_desc_cht),
INTEL_CPU_FAM6(ATOM_AIRMONT_MID,freq_desc_ann),
{}
};
diff --git a/arch/x86/platform/atom/punit_atom_debug.c
b/arch/x86/platform/atom/punit_atom_debug.c
index ee6b0780bea1..52990f68af70 100644
--- a/arch/x86/platform/atom/punit_atom_debug.c
+++ b/arch/x86/platform/atom/punit_atom_debug.c
@@ -125,6 +125,7 @@ static const struct x86_cpu_id intel_punit_cpu_ids[] = {
ICPU(INTEL_FAM6_ATOM_SILVERMONT, punit_device_byt),
