Re: [linux-sunxi] Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-24 Thread icenowy 

在 2017-08-24 14:07，Maxime Ripard 写道：

On Wed, Aug 23, 2017 at 11:13:04PM +0800, icen...@aosc.io wrote:

在 2017-08-23 22:35，Maxime Ripard 写道：
> On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > > +   reg = <0x01c0f000 0x1000>;
> > > > +   clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
> > > > +   clock-names = "ahb", "mmc";
> > > > +   resets = < RST_BUS_MMC0>;
> > > > +   reset-names = "ahb";
> > > > +   pinctrl-0 = <_pins>;
> > > > +   pinctrl-names = "default";
> > > > +   interrupts = ;
> > > > +   max-frequency = <15000>;
> > >
> > > have you tested that frequency?
> >
> > I think the frequency should be kept here, although my cards cannot
> > reach this frequency.
> >
> > The numbers are same as the corresponding controllers in A64.
> >
> > Maybe I should add a comment saying it's educated guess?
>
> I'd rather have it tested by someone, and then add the proper
> frequencies. It took quite a while to figure out how these modes were
> supposed to be working on the A64, so it's not obvious that they're
> just going to work.

Should I add my results here?

MMC0: 25MHz
MMC1: 50MHz
MMC2: 52MHz
MMC3: not wired :-(

I think it's conservative enough and works well ;-)


And that's my point. You didn't test HS200, SDR50 or SDR104 for
example. So you have no idea whether the frequencies from 50MHz to
150MHz are actually working or not.


OK.

I will leave a TODO here, although I cannot measure the frequencies
with Banana Pis -- it will requires custom boards.





>
> > > > +   gic: interrupt-controller@1c81000 {
> > > > +   compatible = "arm,gic-400";
> > > > +   reg = <0x01c81000 0x1000>,
> > > > + <0x01c82000 0x1000>,
> > > > + <0x01c84000 0x2000>,
> > > > + <0x01c86000 0x2000>;
> > > > +   interrupt-controller;
> > > > +   #interrupt-cells = <3>;
> > > > +   interrupts =  > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > +   };
> > > > +   };
> > > > +
> > > > +   timer {
> > > > +   compatible = "arm,armv7-timer";
> > > > +   interrupts =  > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > +,
> > > > +,
> > > > +;
> > >
> > > Those masks are wrong.
> >
> > I compared it with other sun8i SoCs' device tree.
> >
> > Where's wrong?
>
> It's supposed to be a mask of the CPUs in your system. Since you just
> have one of them, it shouldn't be 4.

R40 has 4 cores...

Or I didn't understand this?


Gah, sorry, I mistook this for the V3s for some reason...


Thanks.

I think I should send a fix for V3s.



Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [linux-sunxi] Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-24 Thread icenowy 

在 2017-08-24 14:07，Maxime Ripard 写道：

On Wed, Aug 23, 2017 at 11:13:04PM +0800, icen...@aosc.io wrote:

在 2017-08-23 22:35，Maxime Ripard 写道：
> On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > > +   reg = <0x01c0f000 0x1000>;
> > > > +   clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
> > > > +   clock-names = "ahb", "mmc";
> > > > +   resets = < RST_BUS_MMC0>;
> > > > +   reset-names = "ahb";
> > > > +   pinctrl-0 = <_pins>;
> > > > +   pinctrl-names = "default";
> > > > +   interrupts = ;
> > > > +   max-frequency = <15000>;
> > >
> > > have you tested that frequency?
> >
> > I think the frequency should be kept here, although my cards cannot
> > reach this frequency.
> >
> > The numbers are same as the corresponding controllers in A64.
> >
> > Maybe I should add a comment saying it's educated guess?
>
> I'd rather have it tested by someone, and then add the proper
> frequencies. It took quite a while to figure out how these modes were
> supposed to be working on the A64, so it's not obvious that they're
> just going to work.

Should I add my results here?

MMC0: 25MHz
MMC1: 50MHz
MMC2: 52MHz
MMC3: not wired :-(

I think it's conservative enough and works well ;-)


And that's my point. You didn't test HS200, SDR50 or SDR104 for
example. So you have no idea whether the frequencies from 50MHz to
150MHz are actually working or not.


OK.

I will leave a TODO here, although I cannot measure the frequencies
with Banana Pis -- it will requires custom boards.





>
> > > > +   gic: interrupt-controller@1c81000 {
> > > > +   compatible = "arm,gic-400";
> > > > +   reg = <0x01c81000 0x1000>,
> > > > + <0x01c82000 0x1000>,
> > > > + <0x01c84000 0x2000>,
> > > > + <0x01c86000 0x2000>;
> > > > +   interrupt-controller;
> > > > +   #interrupt-cells = <3>;
> > > > +   interrupts =  > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > +   };
> > > > +   };
> > > > +
> > > > +   timer {
> > > > +   compatible = "arm,armv7-timer";
> > > > +   interrupts =  > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > +,
> > > > +,
> > > > +;
> > >
> > > Those masks are wrong.
> >
> > I compared it with other sun8i SoCs' device tree.
> >
> > Where's wrong?
>
> It's supposed to be a mask of the CPUs in your system. Since you just
> have one of them, it shouldn't be 4.

R40 has 4 cores...

Or I didn't understand this?


Gah, sorry, I mistook this for the V3s for some reason...


Thanks.

I think I should send a fix for V3s.



Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-24 Thread Maxime Ripard 
On Wed, Aug 23, 2017 at 11:13:04PM +0800, icen...@aosc.io wrote:
> 在 2017-08-23 22:35，Maxime Ripard 写道：
> > On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > > > + reg = <0x01c0f000 0x1000>;
> > > > > + clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
> > > > > + clock-names = "ahb", "mmc";
> > > > > + resets = < RST_BUS_MMC0>;
> > > > > + reset-names = "ahb";
> > > > > + pinctrl-0 = <_pins>;
> > > > > + pinctrl-names = "default";
> > > > > + interrupts = ;
> > > > > + max-frequency = <15000>;
> > > >
> > > > have you tested that frequency?
> > > 
> > > I think the frequency should be kept here, although my cards cannot
> > > reach this frequency.
> > > 
> > > The numbers are same as the corresponding controllers in A64.
> > > 
> > > Maybe I should add a comment saying it's educated guess?
> > 
> > I'd rather have it tested by someone, and then add the proper
> > frequencies. It took quite a while to figure out how these modes were
> > supposed to be working on the A64, so it's not obvious that they're
> > just going to work.
> 
> Should I add my results here?
> 
> MMC0: 25MHz
> MMC1: 50MHz
> MMC2: 52MHz
> MMC3: not wired :-(
> 
> I think it's conservative enough and works well ;-)

And that's my point. You didn't test HS200, SDR50 or SDR104 for
example. So you have no idea whether the frequencies from 50MHz to
150MHz are actually working or not.

> 
> > 
> > > > > + gic: interrupt-controller@1c81000 {
> > > > > + compatible = "arm,gic-400";
> > > > > + reg = <0x01c81000 0x1000>,
> > > > > +   <0x01c82000 0x1000>,
> > > > > +   <0x01c84000 0x2000>,
> > > > > +   <0x01c86000 0x2000>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <3>;
> > > > > + interrupts =  > > > > |
> > > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + timer {
> > > > > + compatible = "arm,armv7-timer";
> > > > > + interrupts =  > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > +   > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > +   > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > +   > > > > IRQ_TYPE_LEVEL_LOW)>;
> > > >
> > > > Those masks are wrong.
> > > 
> > > I compared it with other sun8i SoCs' device tree.
> > > 
> > > Where's wrong?
> > 
> > It's supposed to be a mask of the CPUs in your system. Since you just
> > have one of them, it shouldn't be 4.
> 
> R40 has 4 cores...
> 
> Or I didn't understand this?

Gah, sorry, I mistook this for the V3s for some reason...

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-24 Thread Maxime Ripard 
On Wed, Aug 23, 2017 at 11:13:04PM +0800, icen...@aosc.io wrote:
> 在 2017-08-23 22:35，Maxime Ripard 写道：
> > On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > > > + reg = <0x01c0f000 0x1000>;
> > > > > + clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
> > > > > + clock-names = "ahb", "mmc";
> > > > > + resets = < RST_BUS_MMC0>;
> > > > > + reset-names = "ahb";
> > > > > + pinctrl-0 = <_pins>;
> > > > > + pinctrl-names = "default";
> > > > > + interrupts = ;
> > > > > + max-frequency = <15000>;
> > > >
> > > > have you tested that frequency?
> > > 
> > > I think the frequency should be kept here, although my cards cannot
> > > reach this frequency.
> > > 
> > > The numbers are same as the corresponding controllers in A64.
> > > 
> > > Maybe I should add a comment saying it's educated guess?
> > 
> > I'd rather have it tested by someone, and then add the proper
> > frequencies. It took quite a while to figure out how these modes were
> > supposed to be working on the A64, so it's not obvious that they're
> > just going to work.
> 
> Should I add my results here?
> 
> MMC0: 25MHz
> MMC1: 50MHz
> MMC2: 52MHz
> MMC3: not wired :-(
> 
> I think it's conservative enough and works well ;-)

And that's my point. You didn't test HS200, SDR50 or SDR104 for
example. So you have no idea whether the frequencies from 50MHz to
150MHz are actually working or not.

> 
> > 
> > > > > + gic: interrupt-controller@1c81000 {
> > > > > + compatible = "arm,gic-400";
> > > > > + reg = <0x01c81000 0x1000>,
> > > > > +   <0x01c82000 0x1000>,
> > > > > +   <0x01c84000 0x2000>,
> > > > > +   <0x01c86000 0x2000>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <3>;
> > > > > + interrupts =  > > > > |
> > > > > IRQ_TYPE_LEVEL_HIGH)>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + timer {
> > > > > + compatible = "arm,armv7-timer";
> > > > > + interrupts =  > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > +   > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > +   > > > > IRQ_TYPE_LEVEL_LOW)>,
> > > > > +   > > > > IRQ_TYPE_LEVEL_LOW)>;
> > > >
> > > > Those masks are wrong.
> > > 
> > > I compared it with other sun8i SoCs' device tree.
> > > 
> > > Where's wrong?
> > 
> > It's supposed to be a mask of the CPUs in your system. Since you just
> > have one of them, it shouldn't be 4.
> 
> R40 has 4 cores...
> 
> Or I didn't understand this?

Gah, sorry, I mistook this for the V3s for some reason...

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-23 Thread icenowy 

在 2017-08-23 22:35，Maxime Ripard 写道：

On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:

> > + reg = <0x01c0f000 0x1000>;
> > + clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
> > + clock-names = "ahb", "mmc";
> > + resets = < RST_BUS_MMC0>;
> > + reset-names = "ahb";
> > + pinctrl-0 = <_pins>;
> > + pinctrl-names = "default";
> > + interrupts = ;
> > + max-frequency = <15000>;
>
> have you tested that frequency?

I think the frequency should be kept here, although my cards cannot
reach this frequency.

The numbers are same as the corresponding controllers in A64.

Maybe I should add a comment saying it's educated guess?


I'd rather have it tested by someone, and then add the proper
frequencies. It took quite a while to figure out how these modes were
supposed to be working on the A64, so it's not obvious that they're
just going to work.


Should I add my results here?

MMC0: 25MHz
MMC1: 50MHz
MMC2: 52MHz
MMC3: not wired :-(

I think it's conservative enough and works well ;-)




> > + gic: interrupt-controller@1c81000 {
> > + compatible = "arm,gic-400";
> > + reg = <0x01c81000 0x1000>,
> > +   <0x01c82000 0x1000>,
> > +   <0x01c84000 0x2000>,
> > +   <0x01c86000 0x2000>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + interrupts =  > IRQ_TYPE_LEVEL_HIGH)>;
> > + };
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv7-timer";
> > + interrupts =  > IRQ_TYPE_LEVEL_LOW)>,
> > +  ,
> > +  ,
> > +  ;
>
> Those masks are wrong.

I compared it with other sun8i SoCs' device tree.

Where's wrong?


It's supposed to be a mask of the CPUs in your system. Since you just
have one of them, it shouldn't be 4.


R40 has 4 cores...

Or I didn't understand this?



Maxime

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-23 Thread icenowy 

在 2017-08-23 22:35，Maxime Ripard 写道：

On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:

> > + reg = <0x01c0f000 0x1000>;
> > + clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
> > + clock-names = "ahb", "mmc";
> > + resets = < RST_BUS_MMC0>;
> > + reset-names = "ahb";
> > + pinctrl-0 = <_pins>;
> > + pinctrl-names = "default";
> > + interrupts = ;
> > + max-frequency = <15000>;
>
> have you tested that frequency?

I think the frequency should be kept here, although my cards cannot
reach this frequency.

The numbers are same as the corresponding controllers in A64.

Maybe I should add a comment saying it's educated guess?


I'd rather have it tested by someone, and then add the proper
frequencies. It took quite a while to figure out how these modes were
supposed to be working on the A64, so it's not obvious that they're
just going to work.


Should I add my results here?

MMC0: 25MHz
MMC1: 50MHz
MMC2: 52MHz
MMC3: not wired :-(

I think it's conservative enough and works well ;-)




> > + gic: interrupt-controller@1c81000 {
> > + compatible = "arm,gic-400";
> > + reg = <0x01c81000 0x1000>,
> > +   <0x01c82000 0x1000>,
> > +   <0x01c84000 0x2000>,
> > +   <0x01c86000 0x2000>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + interrupts =  > IRQ_TYPE_LEVEL_HIGH)>;
> > + };
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv7-timer";
> > + interrupts =  > IRQ_TYPE_LEVEL_LOW)>,
> > +  ,
> > +  ,
> > +  ;
>
> Those masks are wrong.

I compared it with other sun8i SoCs' device tree.

Where's wrong?


It's supposed to be a mask of the CPUs in your system. Since you just
have one of them, it shouldn't be 4.


R40 has 4 cores...

Or I didn't understand this?



Maxime

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-23 Thread Maxime Ripard 
On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > + reg = <0x01c0f000 0x1000>;
> > > + clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
> > > + clock-names = "ahb", "mmc";
> > > + resets = < RST_BUS_MMC0>;
> > > + reset-names = "ahb";
> > > + pinctrl-0 = <_pins>;
> > > + pinctrl-names = "default";
> > > + interrupts = ;
> > > + max-frequency = <15000>;
> > 
> > have you tested that frequency?
> 
> I think the frequency should be kept here, although my cards cannot
> reach this frequency.
> 
> The numbers are same as the corresponding controllers in A64.
> 
> Maybe I should add a comment saying it's educated guess?

I'd rather have it tested by someone, and then add the proper
frequencies. It took quite a while to figure out how these modes were
supposed to be working on the A64, so it's not obvious that they're
just going to work.

> > > + gic: interrupt-controller@1c81000 {
> > > + compatible = "arm,gic-400";
> > > + reg = <0x01c81000 0x1000>,
> > > +   <0x01c82000 0x1000>,
> > > +   <0x01c84000 0x2000>,
> > > +   <0x01c86000 0x2000>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <3>;
> > > + interrupts =  > > IRQ_TYPE_LEVEL_HIGH)>;
> > > + };
> > > + };
> > > +
> > > + timer {
> > > + compatible = "arm,armv7-timer";
> > > + interrupts =  > > IRQ_TYPE_LEVEL_LOW)>,
> > > +   > > IRQ_TYPE_LEVEL_LOW)>,
> > > +   > > IRQ_TYPE_LEVEL_LOW)>,
> > > +   > > IRQ_TYPE_LEVEL_LOW)>;
> > 
> > Those masks are wrong.
> 
> I compared it with other sun8i SoCs' device tree.
> 
> Where's wrong?

It's supposed to be a mask of the CPUs in your system. Since you just
have one of them, it shouldn't be 4.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-23 Thread Maxime Ripard 
On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > + reg = <0x01c0f000 0x1000>;
> > > + clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
> > > + clock-names = "ahb", "mmc";
> > > + resets = < RST_BUS_MMC0>;
> > > + reset-names = "ahb";
> > > + pinctrl-0 = <_pins>;
> > > + pinctrl-names = "default";
> > > + interrupts = ;
> > > + max-frequency = <15000>;
> > 
> > have you tested that frequency?
> 
> I think the frequency should be kept here, although my cards cannot
> reach this frequency.
> 
> The numbers are same as the corresponding controllers in A64.
> 
> Maybe I should add a comment saying it's educated guess?

I'd rather have it tested by someone, and then add the proper
frequencies. It took quite a while to figure out how these modes were
supposed to be working on the A64, so it's not obvious that they're
just going to work.

> > > + gic: interrupt-controller@1c81000 {
> > > + compatible = "arm,gic-400";
> > > + reg = <0x01c81000 0x1000>,
> > > +   <0x01c82000 0x1000>,
> > > +   <0x01c84000 0x2000>,
> > > +   <0x01c86000 0x2000>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <3>;
> > > + interrupts =  > > IRQ_TYPE_LEVEL_HIGH)>;
> > > + };
> > > + };
> > > +
> > > + timer {
> > > + compatible = "arm,armv7-timer";
> > > + interrupts =  > > IRQ_TYPE_LEVEL_LOW)>,
> > > +   > > IRQ_TYPE_LEVEL_LOW)>,
> > > +   > > IRQ_TYPE_LEVEL_LOW)>,
> > > +   > > IRQ_TYPE_LEVEL_LOW)>;
> > 
> > Those masks are wrong.
> 
> I compared it with other sun8i SoCs' device tree.
> 
> Where's wrong?

It's supposed to be a mask of the CPUs in your system. Since you just
have one of them, it shouldn't be 4.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-23 Thread icenowy 

在 2017-08-23 04:05，Maxime Ripard 写道：

Hi,

On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:

From: Chen-Yu Tsai 

The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Icenowy Zheng 


I'm not sure why you have two series to achieve one thing here. And
the fact that you don't have a cover letter doesn't make it any
clearer.

Please make series based on what you're trying to do and not split it
arbitrarily. And document what you're doing in a cover letter.


---
 arch/arm/boot/dts/sun8i-r40.dtsi | 396 
+++

 1 file changed, 396 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi 
b/arch/arm/boot/dts/sun8i-r40.dtsi

new file mode 100644
index ..5b48801bdd01
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,396 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai 
+ * Copyright 2017 Icenowy Zheng 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of 
the

+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the 
Software.

+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY 
KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 
WARRANTIES

+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
+   };
+
+   osc32k: osc32k {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+   };
+

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-23 Thread icenowy 

在 2017-08-23 04:05，Maxime Ripard 写道：

Hi,

On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:

From: Chen-Yu Tsai 

The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Icenowy Zheng 


I'm not sure why you have two series to achieve one thing here. And
the fact that you don't have a cover letter doesn't make it any
clearer.

Please make series based on what you're trying to do and not split it
arbitrarily. And document what you're doing in a cover letter.


---
 arch/arm/boot/dts/sun8i-r40.dtsi | 396 
+++

 1 file changed, 396 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi 
b/arch/arm/boot/dts/sun8i-r40.dtsi

new file mode 100644
index ..5b48801bdd01
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,396 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai 
+ * Copyright 2017 Icenowy Zheng 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of 
the

+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the 
Software.

+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY 
KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 
WARRANTIES

+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
+   };
+
+   osc32k: osc32k {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   };
+
+   cpu@2 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <2>;
+   };
+
+   cpu@3 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <3>;
+   };
+   };
+
+   soc {
+   compatible = "simple-bus";
+

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-22 Thread Icenowy Zheng 


于 2017年8月23日 GMT+08:00 上午4:05:21, Maxime Ripard 
 写到:
>Hi,
>
>On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai 
>> 
>> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
>> The R40 is a smaller chip than the A20, but features the same set
>> of programmable pins, with a couple extra pins and some new pin
>> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
>> GPU. It retains most if not all features from the A20, while adding
>> some new features, such as MIPI DSI output, or updating various
>> hardware blocks, such as DE 2.0.
>> 
>> Signed-off-by: Chen-Yu Tsai 
>> Signed-off-by: Icenowy Zheng 
>
>I'm not sure why you have two series to achieve one thing here. And
>the fact that you don't have a cover letter doesn't make it any
>clearer.
>
>Please make series based on what you're trying to do and not split it
>arbitrarily. And document what you're doing in a cover letter.
>
>> ---
>>  arch/arm/boot/dts/sun8i-r40.dtsi | 396
>+++
>>  1 file changed, 396 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>> 
>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
>b/arch/arm/boot/dts/sun8i-r40.dtsi
>> new file mode 100644
>> index ..5b48801bdd01
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>> @@ -0,0 +1,396 @@
>> +/*
>> + * Copyright 2017 Chen-Yu Tsai 
>> + * Copyright 2017 Icenowy Zheng 
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this
>dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>as
>> + * published by the Free Software Foundation; either version 2
>of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty
>of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated
>documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom
>the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall
>be
>> + * included in all copies or substantial portions of the
>Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
>KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
>WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/ {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +interrupt-parent = <>;
>> +
>> +clocks {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +ranges;
>> +
>> +osc24M: osc24M {
>> +#clock-cells = <0>;
>> +compatible = "fixed-clock";
>> +clock-frequency = <2400>;
>> +clock-output-names = "osc24M";
>> +};
>> +
>> +osc32k: osc32k {
>> +#clock-cells = <0>;
>> +compatible = "fixed-clock";
>> +clock-frequency = <32768>;
>> +clock-output-names = "osc32k";
>> +};
>> +};
>> +
>> +cpus {
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +
>> +cpu@0 {
>> +compatible = "arm,cortex-a7";
>> +device_type = "cpu";
>> +reg = <0>;
>> +};
>> +
>> +cpu@1 {
>> +compatible = "arm,cortex-a7";
>> +device_type = "cpu";
>> +reg = <1>;
>> +};
>> +
>> +cpu@2 {
>> +compatible =

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-22 Thread Icenowy Zheng 


于 2017年8月23日 GMT+08:00 上午4:05:21, Maxime Ripard 
 写到:
>Hi,
>
>On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai 
>> 
>> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
>> The R40 is a smaller chip than the A20, but features the same set
>> of programmable pins, with a couple extra pins and some new pin
>> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
>> GPU. It retains most if not all features from the A20, while adding
>> some new features, such as MIPI DSI output, or updating various
>> hardware blocks, such as DE 2.0.
>> 
>> Signed-off-by: Chen-Yu Tsai 
>> Signed-off-by: Icenowy Zheng 
>
>I'm not sure why you have two series to achieve one thing here. And
>the fact that you don't have a cover letter doesn't make it any
>clearer.
>
>Please make series based on what you're trying to do and not split it
>arbitrarily. And document what you're doing in a cover letter.
>
>> ---
>>  arch/arm/boot/dts/sun8i-r40.dtsi | 396
>+++
>>  1 file changed, 396 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>> 
>> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
>b/arch/arm/boot/dts/sun8i-r40.dtsi
>> new file mode 100644
>> index ..5b48801bdd01
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
>> @@ -0,0 +1,396 @@
>> +/*
>> + * Copyright 2017 Chen-Yu Tsai 
>> + * Copyright 2017 Icenowy Zheng 
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this
>dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>as
>> + * published by the Free Software Foundation; either version 2
>of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty
>of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated
>documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom
>the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall
>be
>> + * included in all copies or substantial portions of the
>Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
>KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
>WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/ {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +interrupt-parent = <>;
>> +
>> +clocks {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +ranges;
>> +
>> +osc24M: osc24M {
>> +#clock-cells = <0>;
>> +compatible = "fixed-clock";
>> +clock-frequency = <2400>;
>> +clock-output-names = "osc24M";
>> +};
>> +
>> +osc32k: osc32k {
>> +#clock-cells = <0>;
>> +compatible = "fixed-clock";
>> +clock-frequency = <32768>;
>> +clock-output-names = "osc32k";
>> +};
>> +};
>> +
>> +cpus {
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +
>> +cpu@0 {
>> +compatible = "arm,cortex-a7";
>> +device_type = "cpu";
>> +reg = <0>;
>> +};
>> +
>> +cpu@1 {
>> +compatible = "arm,cortex-a7";
>> +device_type = "cpu";
>> +reg = <1>;
>> +};
>> +
>> +cpu@2 {
>> +compatible = "arm,cortex-a7";
>> +device_type = "cpu";
>> +reg = <2>;
>> +};
>> +
>> +

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-22 Thread Maxime Ripard 
Hi,

On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai 
> 
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some new pin
> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
> GPU. It retains most if not all features from the A20, while adding
> some new features, such as MIPI DSI output, or updating various
> hardware blocks, such as DE 2.0.
> 
> Signed-off-by: Chen-Yu Tsai 
> Signed-off-by: Icenowy Zheng 

I'm not sure why you have two series to achieve one thing here. And
the fact that you don't have a cover letter doesn't make it any
clearer.

Please make series based on what you're trying to do and not split it
arbitrarily. And document what you're doing in a cover letter.

> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi | 396 
> +++
>  1 file changed, 396 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi 
> b/arch/arm/boot/dts/sun8i-r40.dtsi
> new file mode 100644
> index ..5b48801bdd01
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,396 @@
> +/*
> + * Copyright 2017 Chen-Yu Tsai 
> + * Copyright 2017 Icenowy Zheng 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <>;
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <2400>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a7";

Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

2017-08-22 Thread Maxime Ripard 
Hi,

On Tue, Aug 22, 2017 at 02:17:40PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai 
> 
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some new pin
> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
> GPU. It retains most if not all features from the A20, while adding
> some new features, such as MIPI DSI output, or updating various
> hardware blocks, such as DE 2.0.
> 
> Signed-off-by: Chen-Yu Tsai 
> Signed-off-by: Icenowy Zheng 

I'm not sure why you have two series to achieve one thing here. And
the fact that you don't have a cover letter doesn't make it any
clearer.

Please make series based on what you're trying to do and not split it
arbitrarily. And document what you're doing in a cover letter.

> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi | 396 
> +++
>  1 file changed, 396 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi 
> b/arch/arm/boot/dts/sun8i-r40.dtsi
> new file mode 100644
> index ..5b48801bdd01
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,396 @@
> +/*
> + * Copyright 2017 Chen-Yu Tsai 
> + * Copyright 2017 Icenowy Zheng 
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <>;
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <2400>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <3>;