Hi Mark,
On Thu, Oct 18, 2018 at 10:26:31PM +0800, Mark Rutland wrote:
> On Thu, Oct 18, 2018 at 04:43:14PM +0800, Nickhu wrote:
> > There two bitfield bug for perfomance counter
> > in bitfield.h:
> >
> > PFM_CTL_offSEL1 21 --> 16
> > PFM_CTL_offSEL2 27 --> 22
> >
> > This commit fix it.
> >
> > Signed-off-by: Nickhu
>
> This patch should probably be move before the patch adding perf support.
> That way, perf support isn't broken at the point it is added.
>
> Thanks,
> Mark.
>
> > ---
> > arch/nds32/include/asm/bitfield.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/nds32/include/asm/bitfield.h
> > b/arch/nds32/include/asm/bitfield.h
> > index 8e84fc385b94..19b2841219ad 100644
> > --- a/arch/nds32/include/asm/bitfield.h
> > +++ b/arch/nds32/include/asm/bitfield.h
> > @@ -692,8 +692,8 @@
> > #define PFM_CTL_offKU1 13 /* Enable user mode event
> > counting for PFMC1 */
> > #define PFM_CTL_offKU2 14 /* Enable user mode event
> > counting for PFMC2 */
> > #define PFM_CTL_offSEL015 /* The event selection for
> > PFMC0 */
> > -#define PFM_CTL_offSEL121 /* The event selection for
> > PFMC1 */
> > -#define PFM_CTL_offSEL227 /* The event selection for
> > PFMC2 */
> > +#define PFM_CTL_offSEL116 /* The event selection for
> > PFMC1 */
> > +#define PFM_CTL_offSEL222 /* The event selection for
> > PFMC2 */
> > /* bit 28:31 reserved */
> >
> > #define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 )
> > --
> > 2.17.0
> >
Thank you for the advice !!
I will prepare another patch for it.
