Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Christian,
On 6/20/2019 9:02 PM, Christian Lamparter wrote:
> Hello Sricharan,
>
> On Wednesday, June 19, 2019 4:42:11 PM CEST Sricharan R wrote:
>> On 6/15/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R wrote:
Hi Christian,
On 6/10/2019 5:45 PM, Christian Lamparter wrote:
> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R
>>> wrote:
Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.
Signed-off-by: Sricharan R
Signed-off-by: Abhishek Sahu
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
>>> Recently-ish, we ran into an issue with the clock-frequency of the
>>> sleep_clk
>>> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
>>> From what I know, the external "32KHz" crystals have 32768 Hz, but the
>>> QSDK
>>> declares them at 32000 Hz. Since you probably have access to the BOM and
>>> datasheets. Can you please confirm what's the real clock frequency for
>>> the IPQ6018.
>>> (And maybe also for the sleep_clk of the IPQ4018 as well?).
>>>
>>
>> What exactly is the issue that you faced ?
>> Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as
>> well.
>
> We need just a confirmation.
>
> Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
>
> | sleep_clk: sleep_clk {
> | compatible = "fixed-clock";
> | clock-frequency = <32768>;
> | #clock-cells = <0>;
> | };
>
>
>
> Which makes sense, because all previous Qualcomm Atheros MIPS and the
> future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
>
> For example: The AR9344 derives the clock from the 25MHz/40MHz external
> oscillator. This is explained in "8.16.9 Derived RTC Clock
> (DERIVED_RTC_CLK)".
> Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
> depending whenever the external reference crystal has 40MHz or 25MHz.
> (1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
> in "10.19.11 Derived RTC Clock".
>
> For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
>
> "I was only able to verify for IPQ8072 that it had a 32.768 KHz
> sleep clock."
>
> So this is pretty much "why there is an issue", it's confusing.
> Is possible can you please look if there are (fixed) divisors values
> listed in the documentation or the registers and bits that the values
> are stored in? Because then we could just calculate it.
>
Really sorry for the confusion. So looking little more, SLEEP_CLK is
derived
from an external 38.4MHZ crystal, it is 32.768 KHZ.
>>> That's really valuable information to have. Thank you!
>>>
Somehow the clk freq plan etc seems to mention them only as .032 MHZ and
misses
out. That means i will correct the patch for 32768 and probably the
ipq8074.dtsi as well
>>>
>>> Ok, there's one more issue that Paul found (at least with the IPQ4019),
>>> https://patchwork.ozlabs.org/patch/1099482
>>>
>>> it seems that the "sleep_clk" node in the qcom-ipq4019.dtsi is not used by
>>> the gcc-ipq4019.c clk driver. this causes both wifi rtc_clks and the usb
>>> sleep
>>> clks to dangle in the /sys/kernel/debug/clk/clk_summary (from a RT-AC58U)
>>>
>>>clock enable_cnt prepare_cntrate
>>> accuracy phase
>>>
>>> xo 994800
>>> 0 0
>>> [...]
>>> sleep_clk11 32768
>>> 0 0
>>> gcc_wcss5g_rtc_clk 11 0
>>> 0 0
>>> gcc_wcss2g_rtc_clk 11 0
>>> 0 0
>>> gcc_usb3_sleep_clk 11 0
>>> 0 0
>>> gcc_usb2_sleep_clk 11 0
>>> 0 0
>>>
>>> with his patch the /sys/kernel/debug/clk/clk_summary looks
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hello Sricharan,
On Wednesday, June 19, 2019 4:42:11 PM CEST Sricharan R wrote:
> On 6/15/2019 2:11 AM, Christian Lamparter wrote:
> > On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R wrote:
> >> Hi Christian,
> >>
> >> On 6/10/2019 5:45 PM, Christian Lamparter wrote:
> >>> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
> Hi Christian,
>
> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
> > On Wed, Jun 5, 2019 at 7:16 PM Sricharan R
> > wrote:
> >>
> >> Add initial device tree support for the Qualcomm IPQ6018 SoC and
> >> CP01 evaluation board.
> >>
> >> Signed-off-by: Sricharan R
> >> Signed-off-by: Abhishek Sahu
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> >>
> >> + clocks {
> >> + sleep_clk: sleep_clk {
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <32000>;
> >> + #clock-cells = <0>;
> >> + };
> >> +
> > Recently-ish, we ran into an issue with the clock-frequency of the
> > sleep_clk
> > on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
> > From what I know, the external "32KHz" crystals have 32768 Hz, but the
> > QSDK
> > declares them at 32000 Hz. Since you probably have access to the BOM and
> > datasheets. Can you please confirm what's the real clock frequency for
> > the IPQ6018.
> > (And maybe also for the sleep_clk of the IPQ4018 as well?).
> >
>
> What exactly is the issue that you faced ?
> Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as
> well.
> >>>
> >>> We need just a confirmation.
> >>>
> >>> Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
> >>>
> >>> | sleep_clk: sleep_clk {
> >>> | compatible = "fixed-clock";
> >>> | clock-frequency = <32768>;
> >>> | #clock-cells = <0>;
> >>> | };
> >>>
> >>>
> >>>
> >>> Which makes sense, because all previous Qualcomm Atheros MIPS and the
> >>> future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
> >>>
> >>> For example: The AR9344 derives the clock from the 25MHz/40MHz external
> >>> oscillator. This is explained in "8.16.9 Derived RTC Clock
> >>> (DERIVED_RTC_CLK)".
> >>> Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
> >>> depending whenever the external reference crystal has 40MHz or 25MHz.
> >>> (1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
> >>> in "10.19.11 Derived RTC Clock".
> >>>
> >>> For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
> >>>
> >>> "I was only able to verify for IPQ8072 that it had a 32.768 KHz
> >>> sleep clock."
> >>>
> >>> So this is pretty much "why there is an issue", it's confusing.
> >>> Is possible can you please look if there are (fixed) divisors values
> >>> listed in the documentation or the registers and bits that the values
> >>> are stored in? Because then we could just calculate it.
> >>>
> >>
> >> Really sorry for the confusion. So looking little more, SLEEP_CLK is
> >> derived
> >> from an external 38.4MHZ crystal, it is 32.768 KHZ.
> > That's really valuable information to have. Thank you!
> >
> >> Somehow the clk freq plan etc seems to mention them only as .032 MHZ and
> >> misses
> >> out. That means i will correct the patch for 32768 and probably the
> >> ipq8074.dtsi as well
> >
> > Ok, there's one more issue that Paul found (at least with the IPQ4019),
> > https://patchwork.ozlabs.org/patch/1099482
> >
> > it seems that the "sleep_clk" node in the qcom-ipq4019.dtsi is not used by
> > the gcc-ipq4019.c clk driver. this causes both wifi rtc_clks and the usb
> > sleep
> > clks to dangle in the /sys/kernel/debug/clk/clk_summary (from a RT-AC58U)
> >
> >clock enable_cnt prepare_cntrate
> > accuracy phase
> >
> > xo 994800
> > 0 0
> > [...]
> > sleep_clk11 32768
> > 0 0
> > gcc_wcss5g_rtc_clk 11 0
> > 0 0
> > gcc_wcss2g_rtc_clk 11 0
> > 0 0
> > gcc_usb3_sleep_clk 11 0
> > 0 0
> > gcc_usb2_sleep_clk 11 0
> > 0 0
> >
> > with his patch the /sys/kernel/debug/clk/clk_summary looks "better"
> >
> > (something like this:)
> >
> >clock
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Christian,
On 6/15/2019 2:11 AM, Christian Lamparter wrote:
> On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/10/2019 5:45 PM, Christian Lamparter wrote:
>>> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
Hi Christian,
On 6/6/2019 2:11 AM, Christian Lamparter wrote:
> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R
> wrote:
>>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>> + clocks {
>> + sleep_clk: sleep_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
>> + #clock-cells = <0>;
>> + };
>> +
> Recently-ish, we ran into an issue with the clock-frequency of the
> sleep_clk
> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
> From what I know, the external "32KHz" crystals have 32768 Hz, but the
> QSDK
> declares them at 32000 Hz. Since you probably have access to the BOM and
> datasheets. Can you please confirm what's the real clock frequency for
> the IPQ6018.
> (And maybe also for the sleep_clk of the IPQ4018 as well?).
>
What exactly is the issue that you faced ?
Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as well.
>>>
>>> We need just a confirmation.
>>>
>>> Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
>>>
>>> | sleep_clk: sleep_clk {
>>> | compatible = "fixed-clock";
>>> | clock-frequency = <32768>;
>>> | #clock-cells = <0>;
>>> | };
>>>
>>>
>>>
>>> Which makes sense, because all previous Qualcomm Atheros MIPS and the
>>> future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
>>>
>>> For example: The AR9344 derives the clock from the 25MHz/40MHz external
>>> oscillator. This is explained in "8.16.9 Derived RTC Clock
>>> (DERIVED_RTC_CLK)".
>>> Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
>>> depending whenever the external reference crystal has 40MHz or 25MHz.
>>> (1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
>>> in "10.19.11 Derived RTC Clock".
>>>
>>> For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
>>>
>>> "I was only able to verify for IPQ8072 that it had a 32.768 KHz
>>> sleep clock."
>>>
>>> So this is pretty much "why there is an issue", it's confusing.
>>> Is possible can you please look if there are (fixed) divisors values
>>> listed in the documentation or the registers and bits that the values
>>> are stored in? Because then we could just calculate it.
>>>
>>
>> Really sorry for the confusion. So looking little more, SLEEP_CLK is derived
>> from an external 38.4MHZ crystal, it is 32.768 KHZ.
> That's really valuable information to have. Thank you!
>
>> Somehow the clk freq plan etc seems to mention them only as .032 MHZ and
>> misses
>> out. That means i will correct the patch for 32768 and probably the
>> ipq8074.dtsi as well
>
> Ok, there's one more issue that Paul found (at least with the IPQ4019),
> https://patchwork.ozlabs.org/patch/1099482
>
> it seems that the "sleep_clk" node in the qcom-ipq4019.dtsi is not used by
> the gcc-ipq4019.c clk driver. this causes both wifi rtc_clks and the usb sleep
> clks to dangle in the /sys/kernel/debug/clk/clk_summary (from a RT-AC58U)
>
>clock enable_cnt prepare_cntrate
> accuracy phase
>
> xo 994800
> 0 0
> [...]
> sleep_clk11 32768
> 0 0
> gcc_wcss5g_rtc_clk 11 0
> 0 0
> gcc_wcss2g_rtc_clk 11 0
> 0 0
> gcc_usb3_sleep_clk 11 0
> 0 0
> gcc_usb2_sleep_clk 11 0
> 0 0
>
> with his patch the /sys/kernel/debug/clk/clk_summary looks "better"
>
> (something like this:)
>
>clock enable_cnt prepare_cntrate
> accuracy phase
>
> xo 994800
> 0 0
> [...]
> gcc_sleep_clk_src
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R wrote:
> Hi Christian,
>
> On 6/10/2019 5:45 PM, Christian Lamparter wrote:
> > On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
> >> Hi Christian,
> >>
> >> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
> >>> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R
> >>> wrote:
>
> Add initial device tree support for the Qualcomm IPQ6018 SoC and
> CP01 evaluation board.
>
> Signed-off-by: Sricharan R
> Signed-off-by: Abhishek Sahu
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>
> + clocks {
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> +
> >>> Recently-ish, we ran into an issue with the clock-frequency of the
> >>> sleep_clk
> >>> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
> >>> From what I know, the external "32KHz" crystals have 32768 Hz, but the
> >>> QSDK
> >>> declares them at 32000 Hz. Since you probably have access to the BOM and
> >>> datasheets. Can you please confirm what's the real clock frequency for
> >>> the IPQ6018.
> >>> (And maybe also for the sleep_clk of the IPQ4018 as well?).
> >>>
> >>
> >> What exactly is the issue that you faced ?
> >> Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as well.
> >
> > We need just a confirmation.
> >
> > Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
> >
> > | sleep_clk: sleep_clk {
> > | compatible = "fixed-clock";
> > | clock-frequency = <32768>;
> > | #clock-cells = <0>;
> > | };
> >
> >
> >
> > Which makes sense, because all previous Qualcomm Atheros MIPS and the
> > future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
> >
> > For example: The AR9344 derives the clock from the 25MHz/40MHz external
> > oscillator. This is explained in "8.16.9 Derived RTC Clock
> > (DERIVED_RTC_CLK)".
> > Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
> > depending whenever the external reference crystal has 40MHz or 25MHz.
> > (1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
> > in "10.19.11 Derived RTC Clock".
> >
> > For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
> >
> > "I was only able to verify for IPQ8072 that it had a 32.768 KHz
> > sleep clock."
> >
> > So this is pretty much "why there is an issue", it's confusing.
> > Is possible can you please look if there are (fixed) divisors values
> > listed in the documentation or the registers and bits that the values
> > are stored in? Because then we could just calculate it.
> >
>
> Really sorry for the confusion. So looking little more, SLEEP_CLK is derived
> from an external 38.4MHZ crystal, it is 32.768 KHZ.
That's really valuable information to have. Thank you!
> Somehow the clk freq plan etc seems to mention them only as .032 MHZ and
> misses
> out. That means i will correct the patch for 32768 and probably the
> ipq8074.dtsi as well
Ok, there's one more issue that Paul found (at least with the IPQ4019),
https://patchwork.ozlabs.org/patch/1099482
it seems that the "sleep_clk" node in the qcom-ipq4019.dtsi is not used by
the gcc-ipq4019.c clk driver. this causes both wifi rtc_clks and the usb sleep
clks to dangle in the /sys/kernel/debug/clk/clk_summary (from a RT-AC58U)
clock enable_cnt prepare_cntrate accuracy
phase
xo 994800 0 0
[...]
sleep_clk11 32768 0
0
gcc_wcss5g_rtc_clk 11 0 0
0
gcc_wcss2g_rtc_clk 11 0 0
0
gcc_usb3_sleep_clk 11 0 0
0
gcc_usb2_sleep_clk 11 0 0
0
with his patch the /sys/kernel/debug/clk/clk_summary looks "better"
(something like this:)
clock enable_cnt prepare_cntrate accuracy
phase
xo 994800 0 0
[...]
gcc_sleep_clk_src55 32000 0
0
gcc_wcss5g_rtc_clk11 32000 0
0
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Christian,
On 6/10/2019 5:45 PM, Christian Lamparter wrote:
> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.
Signed-off-by: Sricharan R
Signed-off-by: Abhishek Sahu
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
>>> Recently-ish, we ran into an issue with the clock-frequency of the sleep_clk
>>> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
>>> From what I know, the external "32KHz" crystals have 32768 Hz, but the QSDK
>>> declares them at 32000 Hz. Since you probably have access to the BOM and
>>> datasheets. Can you please confirm what's the real clock frequency for
>>> the IPQ6018.
>>> (And maybe also for the sleep_clk of the IPQ4018 as well?).
>>>
>>
>> What exactly is the issue that you faced ?
>> Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as well.
>
> We need just a confirmation.
>
> Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
>
> | sleep_clk: sleep_clk {
> | compatible = "fixed-clock";
> | clock-frequency = <32768>;
> | #clock-cells = <0>;
> | };
>
>
>
> Which makes sense, because all previous Qualcomm Atheros MIPS and the
> future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
>
> For example: The AR9344 derives the clock from the 25MHz/40MHz external
> oscillator. This is explained in "8.16.9 Derived RTC Clock (DERIVED_RTC_CLK)".
> Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
> depending whenever the external reference crystal has 40MHz or 25MHz.
> (1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
> in "10.19.11 Derived RTC Clock".
>
> For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
>
> "I was only able to verify for IPQ8072 that it had a 32.768 KHz
> sleep clock."
>
> So this is pretty much "why there is an issue", it's confusing.
> Is possible can you please look if there are (fixed) divisors values
> listed in the documentation or the registers and bits that the values
> are stored in? Because then we could just calculate it.
>
Really sorry for the confusion. So looking little more, SLEEP_CLK is derived
from an external 38.4MHZ crystal, it is 32.768 KHZ. Somehow the
clk freq plan etc seems to mention them only as .032 MHZ and misses
out. That means i will correct the patch for 32768 and probably the
ipq8074.dtsi as well
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Quoting Sricharan R (2019-06-10 08:45:22)
> On 6/8/2019 9:18 AM, Bjorn Andersson wrote:
> > On Wed 05 Jun 10:16 PDT 2019, Sricharan R wrote:
> >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> >> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> >> new file mode 100644
> >> index 000..79cccdd
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> >> +compatible = "fixed-clock";
> >> +clock-frequency = <32000>;
> >> +#clock-cells = <0>;
> >> +};
> >> +
> >> +xo: xo {
> >> +compatible = "fixed-clock";
> >> +clock-frequency = <2400>;
> >> +#clock-cells = <0>;
> >> +};
> >> +
> >> +bias_pll_cc_clk {
> >
> > Please give this a label and reference it from the node that uses it
> > (regardless of the implementation matching by clock name).
> >
> ok, in that case, so might have to remove these for now, till we add
> the corresponding users.
Yes, please remove them. They don't look like board clks, instead
they're SoC level details that need to be created by some clk driver
like GCC.
>
> >> +compatible = "fixed-clock";
> >> +clock-frequency = <3>;
> >> +#clock-cells = <0>;
> >> +};
> >> +
> >> +bias_pll_nss_noc_clk {
> >> +compatible = "fixed-clock";
> >> +clock-frequency = <41650>;
> >> +#clock-cells = <0>;
> >> +};
> >> +
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Bjorn,
On 6/8/2019 9:18 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:16 PDT 2019, Sricharan R wrote:
>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>
> Please fix the order of these (or add a Co-developed-by).
>
ok
>> ---
>> arch/arm64/boot/dts/qcom/Makefile| 1 +
>> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
>> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
>> +++
>> 3 files changed, 267 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index 21d548f..ac22dbb 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -2,6 +2,7 @@
>> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
>
> Sort order.
>
ok
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> new file mode 100644
>> index 000..ac7cb22
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> @@ -0,0 +1,35 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * IPQ6018 CP01 board device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq6018.dtsi"
>> +
>> +/ {
>> +#address-cells = <0x2>;
>> +#size-cells = <0x2>;
>
> This is a count, write it in base 10..
>
ok
>> +model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
>> +compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
>> +interrupt-parent = <>;
>
> Changing #address-cells, #size-cells and interrupt-parent will break the
> dtsi, so I think you should specify them there.
>
ok, will move it to the dtsi.
>> +};
>> +
>> + {
>
> Please sort your nodes based on address, then node name, then label.
>
ok
>> +uart_pins: uart_pins {
>> +mux {
>> +pins = "gpio44", "gpio45";
>> +function = "blsp2_uart";
>> +drive-strength = <8>;
>> +bias-pull-down;
>> +};
>> +};
>> +};
>> +
>> +_uart3 {
>> +pinctrl-0 = <_pins>;
>> +pinctrl-names = "default";
>> +status = "ok";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> new file mode 100644
>> index 000..79cccdd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> @@ -0,0 +1,231 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * IPQ6018 SoC device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ6018";
>> +compatible = "qcom,ipq6018";
>
> No need for model and compatible in the dtsi, these should always be
> specified by the including file.
>
ok, will move it to the dts.
>> +
>> +chosen {
>> +bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
>
> Do you really need console? Can't you use stdout-path?
>
ok, will change.
> And there's no need to specify init=/init.
>
ok.
>> +bootargs-append = " swiotlb=1 clk_ignore_unused";
>
> I'm hoping that you will work on removing the need for
> clk_ignore_unused.
>
hmm, should not be required even now. will remove that.
>> +};
>> +
>> +reserved-memory {
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +ranges;
>> +
>> +tz:tz@4850 {
>
> Space after :
>
ok.
>> +no-map;
>> +reg = <0x0 0x4850 0x0 0x0020>;
>
> I would prefer to have the reg first in these nodes, then the region's
> properties.
>
ok.
>> +};
>> +};
>> +
>> +soc: soc {
>> +#address-cells = <0x1>;
>> +#size-cells = <0x1>;
>> +ranges = <0 0 0 0x>;
>> +dma-ranges;
>> +compatible = "simple-bus";
>> +
>> +intc: interrupt-controller@b00 {
>
> As described above, please sort your nodes based on address, node name
> and lastly label name.
>
ok.
>> +compatible = "qcom,msm-qgic2";
>> +interrupt-controller;
>> +#interrupt-cells = <0x3>;
>> +reg = <0xb00 0x1000>, <0xb002000 0x1000>;
>> +};
>> +
>> +timer {
>>
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
> Hi Christian,
>
> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
> > On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
> >>
> >> Add initial device tree support for the Qualcomm IPQ6018 SoC and
> >> CP01 evaluation board.
> >>
> >> Signed-off-by: Sricharan R
> >> Signed-off-by: Abhishek Sahu
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> >>
> >> + clocks {
> >> + sleep_clk: sleep_clk {
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <32000>;
> >> + #clock-cells = <0>;
> >> + };
> >> +
> > Recently-ish, we ran into an issue with the clock-frequency of the sleep_clk
> > on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
> > From what I know, the external "32KHz" crystals have 32768 Hz, but the QSDK
> > declares them at 32000 Hz. Since you probably have access to the BOM and
> > datasheets. Can you please confirm what's the real clock frequency for
> > the IPQ6018.
> > (And maybe also for the sleep_clk of the IPQ4018 as well?).
> >
>
> What exactly is the issue that you faced ?
> Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as well.
We need just a confirmation.
Then again, Currently the qcom-ipq4019.dtsi is using 32768 Hz.
| sleep_clk: sleep_clk {
| compatible = "fixed-clock";
| clock-frequency = <32768>;
| #clock-cells = <0>;
| };
Which makes sense, because all previous Qualcomm Atheros MIPS and the
future IPQ8072 SoCs have been either using or deriving a 32768 Hz clock.
For example: The AR9344 derives the clock from the 25MHz/40MHz external
oscillator. This is explained in "8.16.9 Derived RTC Clock (DERIVED_RTC_CLK)".
Which mentions that the "32KHz" clock interval is 30.5 usec / 30.48 usec
depending whenever the external reference crystal has 40MHz or 25MHz.
(1/30.5usec = 32.7868852 kilohertz!). The QCA9558 datasheet says the same
in "10.19.11 Derived RTC Clock".
For IPQ8072: I point to the post by Sven Eckelmann on the OpenWrt ML:
"I was only able to verify for IPQ8072 that it had a 32.768 KHz
sleep clock."
So this is pretty much "why there is an issue", it's confusing.
Is possible can you please look if there are (fixed) divisors values
listed in the documentation or the registers and bits that the values
are stored in? Because then we could just calculate it.
Regards,
Christian
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Christian,
On 6/6/2019 2:11 AM, Christian Lamparter wrote:
> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
>>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>> + clocks {
>> + sleep_clk: sleep_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
>> + #clock-cells = <0>;
>> + };
>> +
> Recently-ish, we ran into an issue with the clock-frequency of the sleep_clk
> on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
> From what I know, the external "32KHz" crystals have 32768 Hz, but the QSDK
> declares them at 32000 Hz. Since you probably have access to the BOM and
> datasheets. Can you please confirm what's the real clock frequency for
> the IPQ6018.
> (And maybe also for the sleep_clk of the IPQ4018 as well?).
>
What exactly is the issue that you faced ?
Looking in to the docs, it is <32000> only on ipq6018 and ipq40xx as well.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
On Wed 05 Jun 10:16 PDT 2019, Sricharan R wrote:
> Add initial device tree support for the Qualcomm IPQ6018 SoC and
> CP01 evaluation board.
>
> Signed-off-by: Sricharan R
> Signed-off-by: Abhishek Sahu
Please fix the order of these (or add a Co-developed-by).
> ---
> arch/arm64/boot/dts/qcom/Makefile| 1 +
> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
> +++
> 3 files changed, 267 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile
> b/arch/arm64/boot/dts/qcom/Makefile
> index 21d548f..ac22dbb 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -2,6 +2,7 @@
> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
Sort order.
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> new file mode 100644
> index 000..ac7cb22
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * IPQ6018 CP01 board device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq6018.dtsi"
> +
> +/ {
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
This is a count, write it in base 10..
> + model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
> + compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
> + interrupt-parent = <>;
Changing #address-cells, #size-cells and interrupt-parent will break the
dtsi, so I think you should specify them there.
> +};
> +
> + {
Please sort your nodes based on address, then node name, then label.
> + uart_pins: uart_pins {
> + mux {
> + pins = "gpio44", "gpio45";
> + function = "blsp2_uart";
> + drive-strength = <8>;
> + bias-pull-down;
> + };
> + };
> +};
> +
> +_uart3 {
> + pinctrl-0 = <_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> new file mode 100644
> index 000..79cccdd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -0,0 +1,231 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * IPQ6018 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include
> +#include
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ6018";
> + compatible = "qcom,ipq6018";
No need for model and compatible in the dtsi, these should always be
specified by the including file.
> +
> + chosen {
> + bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
Do you really need console? Can't you use stdout-path?
And there's no need to specify init=/init.
> + bootargs-append = " swiotlb=1 clk_ignore_unused";
I'm hoping that you will work on removing the need for
clk_ignore_unused.
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + tz:tz@4850 {
Space after :
> + no-map;
> + reg = <0x0 0x4850 0x0 0x0020>;
I would prefer to have the reg first in these nodes, then the region's
properties.
> + };
> + };
> +
> + soc: soc {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + ranges = <0 0 0 0x>;
> + dma-ranges;
> + compatible = "simple-bus";
> +
> + intc: interrupt-controller@b00 {
As described above, please sort your nodes based on address, node name
and lastly label name.
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <0x3>;
> + reg = <0xb00 0x1000>, <0xb002000 0x1000>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + timer@b12 {
> + #address-cells = <1>;
> +
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Sudeep,
On 6/5/2019 11:04 PM, Sudeep Holla wrote:
> On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote:
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>> ---
>> arch/arm64/boot/dts/qcom/Makefile| 1 +
>> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
>> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
>> +++
>> 3 files changed, 267 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>
> [...]
>
>> +
>> +CPU3: cpu@3 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53";
>> +enable-method = "psci";
>> +reg = <0x3>;
>> +next-level-cache = <_0>;
>> +};
>> +
>> +L2_0: l2-cache {
>> +compatible = "cache";
>> +cache-level = <0x2>;
>> +};
>> +};
>> +
>> +pmuv8: pmu {
>> +compatible = "arm,armv8-pmuv3";
>
> We know these are Cortex-A53s, why not update these accordingly ?
>
Ok, will change this.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
Hi Marc,
On 6/5/2019 10:56 PM, Marc Zyngier wrote:
> On 05/06/2019 18:16, Sricharan R wrote:
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
>> ---
>> arch/arm64/boot/dts/qcom/Makefile| 1 +
>> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
>> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
>> +++
>> 3 files changed, 267 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index 21d548f..ac22dbb 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -2,6 +2,7 @@
>> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> new file mode 100644
>> index 000..ac7cb22
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
>> @@ -0,0 +1,35 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * IPQ6018 CP01 board device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq6018.dtsi"
>> +
>> +/ {
>> +#address-cells = <0x2>;
>> +#size-cells = <0x2>;
>> +model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
>> +compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
>> +interrupt-parent = <>;
>> +};
>> +
>> + {
>> +uart_pins: uart_pins {
>> +mux {
>> +pins = "gpio44", "gpio45";
>> +function = "blsp2_uart";
>> +drive-strength = <8>;
>> +bias-pull-down;
>> +};
>> +};
>> +};
>> +
>> +_uart3 {
>> +pinctrl-0 = <_pins>;
>> +pinctrl-names = "default";
>> +status = "ok";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> new file mode 100644
>> index 000..79cccdd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> @@ -0,0 +1,231 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * IPQ6018 SoC device tree source
>> + *
>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ6018";
>> +compatible = "qcom,ipq6018";
>> +
>> +chosen {
>> +bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
>> +bootargs-append = " swiotlb=1 clk_ignore_unused";
>> +};
>> +
>> +reserved-memory {
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +ranges;
>> +
>> +tz:tz@4850 {
>> +no-map;
>> +reg = <0x0 0x4850 0x0 0x0020>;
>> +};
>> +};
>> +
>> +soc: soc {
>> +#address-cells = <0x1>;
>> +#size-cells = <0x1>;
>> +ranges = <0 0 0 0x>;
>> +dma-ranges;
>> +compatible = "simple-bus";
>> +
>> +intc: interrupt-controller@b00 {
>> +compatible = "qcom,msm-qgic2";
>> +interrupt-controller;
>> +#interrupt-cells = <0x3>;
>> +reg = <0xb00 0x1000>, <0xb002000 0x1000>;
>
> Where are the rest of the GICv2 MMIO regions, such as GICV and GICH? And
> the maintenance interrupt?
>
GICH - 0xB001000 -- 0xB002000
GICV - 0xB004000 -- 0xB005000
Will add this and the PPI as well.
Regards,
Sricharan
>> +};
>> +
>> +timer {
>> +compatible = "arm,armv8-timer";
>> +interrupts = > IRQ_TYPE_LEVEL_LOW)>,
>> + > IRQ_TYPE_LEVEL_LOW)>,
>> + > IRQ_TYPE_LEVEL_LOW)>,
>> + > IRQ_TYPE_LEVEL_LOW)>;
>
> The fact that you expose the EL2 timer interrupt would tend to confirm
> the idea that this system supports virtualization... Hence my questions
> above.
>
> Thanks,
>
> M.
>
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
>
> Add initial device tree support for the Qualcomm IPQ6018 SoC and
> CP01 evaluation board.
>
> Signed-off-by: Sricharan R
> Signed-off-by: Abhishek Sahu
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>
> + clocks {
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> +
Recently-ish, we ran into an issue with the clock-frequency of the sleep_clk
on older IPQ40XX (and IPQ806x) on the OpenWrt Github and ML.
>From what I know, the external "32KHz" crystals have 32768 Hz, but the QSDK
declares them at 32000 Hz. Since you probably have access to the BOM and
datasheets. Can you please confirm what's the real clock frequency for
the IPQ6018.
(And maybe also for the sleep_clk of the IPQ4018 as well?).
Cheers,
Christian
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote:
> Add initial device tree support for the Qualcomm IPQ6018 SoC and
> CP01 evaluation board.
>
> Signed-off-by: Sricharan R
> Signed-off-by: Abhishek Sahu
> ---
> arch/arm64/boot/dts/qcom/Makefile| 1 +
> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
> +++
> 3 files changed, 267 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>
[...]
> +
> + CPU3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x3>;
> + next-level-cache = <_0>;
> + };
> +
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <0x2>;
> + };
> + };
> +
> + pmuv8: pmu {
> + compatible = "arm,armv8-pmuv3";
We know these are Cortex-A53s, why not update these accordingly ?
--
Regards,
Sudeep
Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
On 05/06/2019 18:16, Sricharan R wrote:
> Add initial device tree support for the Qualcomm IPQ6018 SoC and
> CP01 evaluation board.
>
> Signed-off-by: Sricharan R
> Signed-off-by: Abhishek Sahu
> ---
> arch/arm64/boot/dts/qcom/Makefile| 1 +
> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
> arch/arm64/boot/dts/qcom/ipq6018.dtsi| 231
> +++
> 3 files changed, 267 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile
> b/arch/arm64/boot/dts/qcom/Makefile
> index 21d548f..ac22dbb 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -2,6 +2,7 @@
> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> new file mode 100644
> index 000..ac7cb22
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * IPQ6018 CP01 board device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq6018.dtsi"
> +
> +/ {
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> + model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
> + compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
> + interrupt-parent = <>;
> +};
> +
> + {
> + uart_pins: uart_pins {
> + mux {
> + pins = "gpio44", "gpio45";
> + function = "blsp2_uart";
> + drive-strength = <8>;
> + bias-pull-down;
> + };
> + };
> +};
> +
> +_uart3 {
> + pinctrl-0 = <_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> new file mode 100644
> index 000..79cccdd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -0,0 +1,231 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * IPQ6018 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include
> +#include
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ6018";
> + compatible = "qcom,ipq6018";
> +
> + chosen {
> + bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
> + bootargs-append = " swiotlb=1 clk_ignore_unused";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + tz:tz@4850 {
> + no-map;
> + reg = <0x0 0x4850 0x0 0x0020>;
> + };
> + };
> +
> + soc: soc {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + ranges = <0 0 0 0x>;
> + dma-ranges;
> + compatible = "simple-bus";
> +
> + intc: interrupt-controller@b00 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <0x3>;
> + reg = <0xb00 0x1000>, <0xb002000 0x1000>;
Where are the rest of the GICv2 MMIO regions, such as GICV and GICH? And
the maintenance interrupt?
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>;
The fact that you expose the EL2 timer interrupt would tend to confirm
the idea that this system supports virtualization... Hence my questions
above.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
