Re: [PATCH net-next v1 1/1] stmmac: intel: Drop duplicate ID in the list of PCI device IDs

2021-04-06 Thread patchwork-bot+netdevbpf 
Hello:

This patch was applied to netdev/net-next.git (refs/heads/master):

On Tue,  6 Apr 2021 13:13:06 +0300 you wrote:
> The PCI device IDs are defined with a prefix PCI_DEVICE_ID.
> There is no need to repeat the ID part at the end of each definition.
> 
> Signed-off-by: Andy Shevchenko 
> ---
>  .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 60 +--
>  1 file changed, 30 insertions(+), 30 deletions(-)

Here is the summary with links:
  - [net-next,v1,1/1] stmmac: intel: Drop duplicate ID in the list of PCI 
device IDs
https://git.kernel.org/netdev/net-next/c/3036ec035c4d

You are awesome, thank you!
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Re: [PATCH net-next v1 1/1] stmmac: intel: Drop duplicate ID in the list of PCI device IDs

2021-04-06 Thread Wong Vee Khee 
On Tue, Apr 06, 2021 at 01:13:06PM +0300, Andy Shevchenko wrote:
> The PCI device IDs are defined with a prefix PCI_DEVICE_ID.
> There is no need to repeat the ID part at the end of each definition.
> 
> Signed-off-by: Andy Shevchenko 

Reviewed-by: Wong Vee Khee 

> ---
>  .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 60 +--
>  1 file changed, 30 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c 
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> index 3d9a57043af2..7f0ce373a63d 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
> @@ -1053,41 +1053,41 @@ static int __maybe_unused intel_eth_pci_resume(struct 
> device *dev)
>  static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
>intel_eth_pci_resume);
>  
> -#define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
> -#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID   0x4b30
> -#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID   0x4b31
> -#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID  0x4b32
> +#define PCI_DEVICE_ID_INTEL_QUARK0x0937
> +#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G  0x4b30
> +#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G  0x4b31
> +#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
>  /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
>   * which are named PSE0 and PSE1
>   */
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID  0x4ba0
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID  0x4ba1
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID  0x4bb0
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID  0x4bb1
> -#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2
> -#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID0x43ac
> -#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID0x43a2
> -#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID   0xa0ac
> -#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID0x7aac
> -#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID0x7aad
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G50x4ba2
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
> +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G50x4bb2
> +#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0   0x43ac
> +#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1   0x43a2
> +#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G  0xa0ac
> +#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0   0x7aac
> +#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1   0x7aad
>  
>  static const struct pci_device_id intel_eth_pci_id_table[] = {
> - { PCI_DEVICE_DATA(INTEL, QUARK_ID, _info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, _rgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, _sgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, _sgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, _pse0_rgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, _pse0_sgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, _pse0_sgmii1g_info) 
> },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, _pse1_rgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, _pse1_sgmii1g_info) },
> - { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, _pse1_sgmii1g_info) 
> },
> - { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, _sgmii1g_phy0_info) },
> - { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, _sgmii1g_phy0_info) },
> - { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, _sgmii1g_phy1_info) },
> - { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, _sgmii1g_phy0_info) },
> - { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, _sgmii1g_phy1_info) },
> + { PCI_DEVICE_DATA(INTEL, QUARK, _info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, _rgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, _sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, _sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, _pse0_rgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, _pse0_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, _pse0_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, _pse1_rgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, _pse1_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, _pse1_sgmii1g_info) },
> + { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, _sgmii1g_phy0_info) },
> + { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, _sgmii1g_phy0_info) },
> + { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, _sgmii1g_phy1_info) },
> + { PCI_DEVICE_DATA(INTEL,