Re: [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote: > Use devm_platform_ioremap_resource_byname() to simplify codes. > it contains platform_get_resource_byname() and devm_ioremap_resource(). > > Signed-off-by: Dejin Zheng > --- > v1 -> v2: > - Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c > Due to my mistakes, my patch will modify pcie-xilinx-nwl.c, > but it still need to use the res variable, but > devm_platform_ioremap_resource_byname() funtion can't assign a > value to the variable res. kbuild test robot report it. Thanks > very much for kbuild test robot . > > drivers/pci/controller/cadence/pcie-cadence-ep.c | 3 +-- > drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +-- > drivers/pci/controller/pci-tegra.c | 8 +++- > drivers/pci/controller/pci-xgene.c | 3 +-- > drivers/pci/controller/pcie-altera-msi.c | 3 +-- > drivers/pci/controller/pcie-altera.c | 9 +++-- > drivers/pci/controller/pcie-mediatek.c | 4 +--- > drivers/pci/controller/pcie-rockchip.c | 5 ++--- > 8 files changed, 13 insertions(+), 25 deletions(-) > hey, I found that recent kernels fail to initialize PCI devices on our HP m400 Moonshot cartridges, which are based on the X-Gene SoC. I bisected the issue down to this commit. I found that just reverting this hunk in pci-xgene.c is enough to get v5.12 rcs booting again: > diff --git a/drivers/pci/controller/pci-xgene.c > b/drivers/pci/controller/pci-xgene.c > index d1efa8ffbae1..1431a18eb02c 100644 > --- a/drivers/pci/controller/pci-xgene.c > +++ b/drivers/pci/controller/pci-xgene.c > @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port > *port, > if (IS_ERR(port->csr_base)) > return PTR_ERR(port->csr_base); > > - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); > - port->cfg_base = devm_ioremap_resource(dev, res); > + port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); > if (IS_ERR(port->cfg_base)) > return PTR_ERR(port->cfg_base); > port->cfg_addr = res->start; In case it helps, here's the PCI initialization portion of dmesg when it fails: [0.756359] xgene-pcie 1f50.pcie: host bridge /soc/pcie@1f50 ranges: [0.756372] xgene-pcie 1f50.pcie: No bus range found for /soc/pcie@1f50, using [bus 00-ff] [0.756387] xgene-pcie 1f50.pcie: MEM 0xa13000..0xa1afff -> 0x003000 [0.756404] xgene-pcie 1f50.pcie: IB MEM 0x40..0x7f -> 0x40 [0.756459] xgene-pcie 1f50.pcie: (rc) x8 gen-2 link up [0.756525] xgene-pcie 1f50.pcie: PCI host bridge to bus :00 [0.756532] pci_bus :00: root bus resource [bus 00-ff] [0.756538] pci_bus :00: root bus resource [mem 0xa13000-0xa1afff] (bus address [0x3000-0xafff]) and here's what it looks like when it works: [0.756793] xgene-pcie 1f50.pcie: host bridge /soc/pcie@1f50 ranges: [0.756807] xgene-pcie 1f50.pcie: No bus range found for /soc/pcie@1f50, using [bus 00-ff] [0.756822] xgene-pcie 1f50.pcie: MEM 0xa13000..0xa1afff -> 0x003000 [0.756838] xgene-pcie 1f50.pcie: IB MEM 0x40..0x7f -> 0x40 [0.756892] xgene-pcie 1f50.pcie: (rc) x8 gen-2 link up [0.756962] xgene-pcie 1f50.pcie: PCI host bridge to bus :00 [0.756968] pci_bus :00: root bus resource [bus 00-ff] [0.756974] pci_bus :00: root bus resource [mem 0xa13000-0xa1afff] (bus address [0x3000-0xafff]) [0.757006] pci :00:00.0: [10e8:e004] type 01 class 0x060400 [0.757014] pci_bus :00: 2-byte config write to :00:00.0 offset 0x4 may corrupt adjacent RW1C bits [0.757022] pci_bus :00: 2-byte config write to :00:00.0 offset 0x4 may corrupt adjacent RW1C bits [0.757032] pci_bus :00: 2-byte config write to :00:00.0 offset 0x4 may corrupt adjacent RW1C bits [0.757039] pci_bus :00: 2-byte config write to :00:00.0 offset 0x4 may corrupt adjacent RW1C bits [0.757046] pci_bus :00: 2-byte config write to :00:00.0 offset 0x4 may corrupt adjacent RW1C bits [0.757052] pci_bus :00: 2-byte config write to :00:00.0 offset 0x4 may corrupt adjacent RW1C bits [0.757059] pci_bus :00: 2-byte config write to :00:00.0 offset 0x4 may corrupt adjacent RW1C bits [0.757068] pci_bus :00: 2-byte config write to :00:00.0 offset 0x4 may corrupt adjacent RW1C bits [0.757094] pci_bus :00: 2-byte config write to :00:00.0 offset 0x3e may corrupt adjacent RW1C bits [0.757143] pci :00:00.0: supports D1 D2 [0.757589] pci_bus :00: 2-byte config write to :00:00.0 offset 0x3e may corrupt adjacent RW1C bits [0.757968] pci :01:00.0: [15b3:1007]
Re: [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
On Sat, Mar 27, 2021 at 12:02:42PM -0600, dann frazier wrote: Hi Dann, I'm so sorry for that, And there is a mistake with my patch that caused this problem. Thank you very much for telling me this, I will fix it as soon as possible. > On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote: > > Use devm_platform_ioremap_resource_byname() to simplify codes. > > it contains platform_get_resource_byname() and devm_ioremap_resource(). > > > > Signed-off-by: Dejin Zheng > > --- > > v1 -> v2: > > - Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c > > Due to my mistakes, my patch will modify pcie-xilinx-nwl.c, > > but it still need to use the res variable, but > > devm_platform_ioremap_resource_byname() funtion can't assign a > > value to the variable res. kbuild test robot report it. Thanks > > very much for kbuild test robot . > > > > drivers/pci/controller/cadence/pcie-cadence-ep.c | 3 +-- > > drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +-- > > drivers/pci/controller/pci-tegra.c | 8 +++- > > drivers/pci/controller/pci-xgene.c | 3 +-- > > drivers/pci/controller/pcie-altera-msi.c | 3 +-- > > drivers/pci/controller/pcie-altera.c | 9 +++-- > > drivers/pci/controller/pcie-mediatek.c | 4 +--- > > drivers/pci/controller/pcie-rockchip.c | 5 ++--- > > 8 files changed, 13 insertions(+), 25 deletions(-) > > > > hey, > I found that recent kernels fail to initialize PCI devices on our HP > m400 Moonshot cartridges, which are based on the X-Gene SoC. I > bisected the issue down to this commit. I found that just reverting > this hunk in pci-xgene.c is enough to get v5.12 rcs booting again: > > > diff --git a/drivers/pci/controller/pci-xgene.c > > b/drivers/pci/controller/pci-xgene.c > > index d1efa8ffbae1..1431a18eb02c 100644 > > --- a/drivers/pci/controller/pci-xgene.c > > +++ b/drivers/pci/controller/pci-xgene.c > > @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port > > *port, > > if (IS_ERR(port->csr_base)) > > return PTR_ERR(port->csr_base); > > > > - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); > > - port->cfg_base = devm_ioremap_resource(dev, res); > > + port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); > > if (IS_ERR(port->cfg_base)) > > return PTR_ERR(port->cfg_base); > > port->cfg_addr = res->start; The mistake of this patch is here, port->cfg_addr need the res->start, But this patch remove the res of get "cfg" resource. here use the wrong data by get "csr" resource in the previous. BR, Dejin > > > In case it helps, here's the PCI initialization portion of dmesg when > it fails: > > [0.756359] xgene-pcie 1f50.pcie: host bridge /soc/pcie@1f50 > ranges: > [0.756372] xgene-pcie 1f50.pcie: No bus range found for > /soc/pcie@1f50, using [bus 00-ff] > [0.756387] xgene-pcie 1f50.pcie: MEM 0xa13000..0xa1afff > -> 0x003000 > [0.756404] xgene-pcie 1f50.pcie: IB MEM 0x40..0x7f > -> 0x40 > [0.756459] xgene-pcie 1f50.pcie: (rc) x8 gen-2 link up > [0.756525] xgene-pcie 1f50.pcie: PCI host bridge to bus :00 > [0.756532] pci_bus :00: root bus resource [bus 00-ff] > [0.756538] pci_bus :00: root bus resource [mem > 0xa13000-0xa1afff] (bus address [0x3000-0xafff]) > > > and here's what it looks like when it works: > > [0.756793] xgene-pcie 1f50.pcie: host bridge /soc/pcie@1f50 > ranges: > [0.756807] xgene-pcie 1f50.pcie: No bus range found for > /soc/pcie@1f50, using [bus 00-ff] > [0.756822] xgene-pcie 1f50.pcie: MEM 0xa13000..0xa1afff > -> 0x003000 > [0.756838] xgene-pcie 1f50.pcie: IB MEM 0x40..0x7f > -> 0x40 > [0.756892] xgene-pcie 1f50.pcie: (rc) x8 gen-2 link up > [0.756962] xgene-pcie 1f50.pcie: PCI host bridge to bus :00 > [0.756968] pci_bus :00: root bus resource [bus 00-ff] > [0.756974] pci_bus :00: root bus resource [mem > 0xa13000-0xa1afff] (bus address [0x3000-0xafff]) > [0.757006] pci :00:00.0: [10e8:e004] type 01 class 0x060400 > [0.757014] pci_bus :00: 2-byte config write to :00:00.0 offset > 0x4 may corrupt adjacent RW1C bits > [0.757022] pci_bus :00: 2-byte config write to :00:00.0 offset > 0x4 may corrupt adjacent RW1C bits > [0.757032] pci_bus :00: 2-byte config write to :00:00.0 offset > 0x4 may corrupt adjacent RW1C bits > [0.757039] pci_bus :00: 2-byte config write to :00:00.0 offset > 0x4 may corrupt adjacent RW1C bits > [0.757046] pci_bus :00: 2-byte config write to :00:00.0 offset > 0x4 may corrupt adjacent RW1C bits > [0.757052] pci_bus :00: 2-byte config write to
Re: [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote:
> Use devm_platform_ioremap_resource_byname() to simplify codes.
> it contains platform_get_resource_byname() and devm_ioremap_resource().
>
> Signed-off-by: Dejin Zheng
> ---
> v1 -> v2:
> - Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c
> Due to my mistakes, my patch will modify pcie-xilinx-nwl.c,
> but it still need to use the res variable, but
> devm_platform_ioremap_resource_byname() funtion can't assign a
> value to the variable res. kbuild test robot report it. Thanks
> very much for kbuild test robot .
>
> drivers/pci/controller/cadence/pcie-cadence-ep.c | 3 +--
> drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
> drivers/pci/controller/pci-tegra.c | 8 +++-
> drivers/pci/controller/pci-xgene.c | 3 +--
> drivers/pci/controller/pcie-altera-msi.c | 3 +--
> drivers/pci/controller/pcie-altera.c | 9 +++--
> drivers/pci/controller/pcie-mediatek.c | 4 +---
> drivers/pci/controller/pcie-rockchip.c | 5 ++---
> 8 files changed, 13 insertions(+), 25 deletions(-)
Applied to pci/dwc with Rob and Gustavo's tags (next time please
carry them over and send v2 in-reply-to v1 so that I can follow
it), thanks.
Lorenzo
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index 1c15c8352125..74ffa03fde5f 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -408,8 +408,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
>
> pcie->is_rc = false;
>
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> - pcie->reg_base = devm_ioremap_resource(dev, res);
> + pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
> if (IS_ERR(pcie->reg_base)) {
> dev_err(dev, "missing \"reg\"\n");
> return PTR_ERR(pcie->reg_base);
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
> b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 8c2543f28ba0..dcc460a54875 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -225,8 +225,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> rc->device_id = 0x;
> of_property_read_u32(np, "device-id", &rc->device_id);
>
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> - pcie->reg_base = devm_ioremap_resource(dev, res);
> + pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
> if (IS_ERR(pcie->reg_base)) {
> dev_err(dev, "missing \"reg\"\n");
> return PTR_ERR(pcie->reg_base);
> diff --git a/drivers/pci/controller/pci-tegra.c
> b/drivers/pci/controller/pci-tegra.c
> index e3e917243e10..3e608383df66 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -1462,7 +1462,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie
> *pcie)
> {
> struct device *dev = pcie->dev;
> struct platform_device *pdev = to_platform_device(dev);
> - struct resource *pads, *afi, *res;
> + struct resource *res;
> const struct tegra_pcie_soc *soc = pcie->soc;
> int err;
>
> @@ -1486,15 +1486,13 @@ static int tegra_pcie_get_resources(struct tegra_pcie
> *pcie)
> }
> }
>
> - pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
> - pcie->pads = devm_ioremap_resource(dev, pads);
> + pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
> if (IS_ERR(pcie->pads)) {
> err = PTR_ERR(pcie->pads);
> goto phys_put;
> }
>
> - afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
> - pcie->afi = devm_ioremap_resource(dev, afi);
> + pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
> if (IS_ERR(pcie->afi)) {
> err = PTR_ERR(pcie->afi);
> goto phys_put;
> diff --git a/drivers/pci/controller/pci-xgene.c
> b/drivers/pci/controller/pci-xgene.c
> index d1efa8ffbae1..1431a18eb02c 100644
> --- a/drivers/pci/controller/pci-xgene.c
> +++ b/drivers/pci/controller/pci-xgene.c
> @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port
> *port,
> if (IS_ERR(port->csr_base))
> return PTR_ERR(port->csr_base);
>
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> - port->cfg_base = devm_ioremap_resource(dev, res);
> + port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
> if (IS_ERR(port->cfg_base))
> return PTR_ERR(port->cfg_base);
> port->cfg_addr = res->start;
> diff --git a/drivers/pci/controller/pcie-altera-msi.c
> b/drivers/pci/
Re: [PATCH v2] PCI: controller: convert to devm_platform_ioremap_resource_byname()
On Tue, Jul 07, 2020 at 12:31:17PM +0100, Lorenzo Pieralisi wrote:
> On Wed, Jun 03, 2020 at 01:16:01AM +0800, Dejin Zheng wrote:
> > Use devm_platform_ioremap_resource_byname() to simplify codes.
> > it contains platform_get_resource_byname() and devm_ioremap_resource().
> >
> > Signed-off-by: Dejin Zheng
> > ---
> > v1 -> v2:
> > - Discard changes to the file drivers/pci/controller/pcie-xilinx-nwl.c
> > Due to my mistakes, my patch will modify pcie-xilinx-nwl.c,
> > but it still need to use the res variable, but
> > devm_platform_ioremap_resource_byname() funtion can't assign a
> > value to the variable res. kbuild test robot report it. Thanks
> > very much for kbuild test robot .
> >
> > drivers/pci/controller/cadence/pcie-cadence-ep.c | 3 +--
> > drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
> > drivers/pci/controller/pci-tegra.c | 8 +++-
> > drivers/pci/controller/pci-xgene.c | 3 +--
> > drivers/pci/controller/pcie-altera-msi.c | 3 +--
> > drivers/pci/controller/pcie-altera.c | 9 +++--
> > drivers/pci/controller/pcie-mediatek.c | 4 +---
> > drivers/pci/controller/pcie-rockchip.c | 5 ++---
> > 8 files changed, 13 insertions(+), 25 deletions(-)
>
> Applied to pci/dwc with Rob and Gustavo's tags (next time please
> carry them over and send v2 in-reply-to v1 so that I can follow
> it), thanks.
Moved to pci/misc since it is not really dwc related, apologies.
Lorenzo
> Lorenzo
>
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > index 1c15c8352125..74ffa03fde5f 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > @@ -408,8 +408,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
> >
> > pcie->is_rc = false;
> >
> > - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> > - pcie->reg_base = devm_ioremap_resource(dev, res);
> > + pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
> > if (IS_ERR(pcie->reg_base)) {
> > dev_err(dev, "missing \"reg\"\n");
> > return PTR_ERR(pcie->reg_base);
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > index 8c2543f28ba0..dcc460a54875 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > @@ -225,8 +225,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> > rc->device_id = 0x;
> > of_property_read_u32(np, "device-id", &rc->device_id);
> >
> > - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> > - pcie->reg_base = devm_ioremap_resource(dev, res);
> > + pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
> > if (IS_ERR(pcie->reg_base)) {
> > dev_err(dev, "missing \"reg\"\n");
> > return PTR_ERR(pcie->reg_base);
> > diff --git a/drivers/pci/controller/pci-tegra.c
> > b/drivers/pci/controller/pci-tegra.c
> > index e3e917243e10..3e608383df66 100644
> > --- a/drivers/pci/controller/pci-tegra.c
> > +++ b/drivers/pci/controller/pci-tegra.c
> > @@ -1462,7 +1462,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie
> > *pcie)
> > {
> > struct device *dev = pcie->dev;
> > struct platform_device *pdev = to_platform_device(dev);
> > - struct resource *pads, *afi, *res;
> > + struct resource *res;
> > const struct tegra_pcie_soc *soc = pcie->soc;
> > int err;
> >
> > @@ -1486,15 +1486,13 @@ static int tegra_pcie_get_resources(struct
> > tegra_pcie *pcie)
> > }
> > }
> >
> > - pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
> > - pcie->pads = devm_ioremap_resource(dev, pads);
> > + pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
> > if (IS_ERR(pcie->pads)) {
> > err = PTR_ERR(pcie->pads);
> > goto phys_put;
> > }
> >
> > - afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
> > - pcie->afi = devm_ioremap_resource(dev, afi);
> > + pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
> > if (IS_ERR(pcie->afi)) {
> > err = PTR_ERR(pcie->afi);
> > goto phys_put;
> > diff --git a/drivers/pci/controller/pci-xgene.c
> > b/drivers/pci/controller/pci-xgene.c
> > index d1efa8ffbae1..1431a18eb02c 100644
> > --- a/drivers/pci/controller/pci-xgene.c
> > +++ b/drivers/pci/controller/pci-xgene.c
> > @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port
> > *port,
> > if (IS_ERR(port->csr_base))
> > return PTR_ERR(port->csr_base);
> >
> > - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> > - port->cfg_base = devm_ioremap_resource(dev, res);
> > + por
