On Fri, Apr 5, 2019 at 4:51 AM Ioana Ciornei wrote:
>
> This patch adds DPAA2 MC and AIOP console log support.
>
> The platform driver probes on the "fsl,dpaa2-console" device tree node
> which describes the base firmware address needed in order to infer the
> start address of both firmware logs: MC and AIOP.
> It then exports two misc char devices which can be used to dump
> the needed logs.
>
> Signed-off-by: Ioana Ciornei
> Signed-off-by: Roy Pledge
Applied to soc-fsl for next. Thanks.
> ---
> Changes in v2:
> - adjust the COMPILE_TEST dependencies
> - remove the duplicate "dpaa2-console" print prefix
> - move driver description and author at the bottom
> - do not leak 'cd' structure in _open
>
> drivers/soc/fsl/Kconfig | 10 ++
> drivers/soc/fsl/Makefile| 1 +
> drivers/soc/fsl/dpaa2-console.c | 312
>
> 3 files changed, 323 insertions(+)
> create mode 100644 drivers/soc/fsl/dpaa2-console.c
>
> diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
> index 61f8e1433d0a..b6804c04e96f 100644
> --- a/drivers/soc/fsl/Kconfig
> +++ b/drivers/soc/fsl/Kconfig
> @@ -29,4 +29,14 @@ config FSL_MC_DPIO
> other DPAA2 objects. This driver does not expose the DPIO
> objects individually, but groups them under a service layer
> API.
> +
> +config DPAA2_CONSOLE
> + tristate "QorIQ DPAA2 console driver"
> + depends on OF && (ARCH_LAYERSCAPE || COMPILE_TEST)
> + default y
> + help
> + Console driver for DPAA2 platforms. Exports 2 char devices,
> + /dev/dpaa2_mc_console and /dev/dpaa2_aiop_console,
> + which can be used to dump the Management Complex and AIOP
> + firmware logs.
> endmenu
> diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
> index 803ef1bfb5ff..57762c9fc7da 100644
> --- a/drivers/soc/fsl/Makefile
> +++ b/drivers/soc/fsl/Makefile
> @@ -7,3 +7,4 @@ obj-$(CONFIG_QUICC_ENGINE) += qe/
> obj-$(CONFIG_CPM) += qe/
> obj-$(CONFIG_FSL_GUTS) += guts.o
> obj-$(CONFIG_FSL_MC_DPIO) += dpio/
> +obj-$(CONFIG_DPAA2_CONSOLE)+= dpaa2-console.o
> diff --git a/drivers/soc/fsl/dpaa2-console.c b/drivers/soc/fsl/dpaa2-console.c
> new file mode 100644
> index ..37e582e818d3
> --- /dev/null
> +++ b/drivers/soc/fsl/dpaa2-console.c
> @@ -0,0 +1,312 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Freescale DPAA2 Platforms Console Driver
> + *
> + * Copyright 2015-2016 Freescale Semiconductor Inc.
> + * Copyright 2018 NXP
> + */
> +
> +#define pr_fmt(fmt) "dpaa2-console: " fmt
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* MC firmware base low/high registers indexes */
> +#define MCFBALR_OFFSET 0
> +#define MCFBAHR_OFFSET 1
> +
> +/* Bit masks used to get the most/least significant part of the MC base addr
> */
> +#define MC_FW_ADDR_MASK_HIGH 0x1
> +#define MC_FW_ADDR_MASK_LOW 0xE000
> +
> +#define MC_BUFFER_OFFSET 0x0100
> +#define MC_BUFFER_SIZE (1024 * 1024 * 16)
> +#define MC_OFFSET_DELTA MC_BUFFER_OFFSET
> +
> +#define AIOP_BUFFER_OFFSET 0x0600
> +#define AIOP_BUFFER_SIZE (1024 * 1024 * 16)
> +#define AIOP_OFFSET_DELTA 0
> +
> +#define LOG_HEADER_FLAG_BUFFER_WRAPAROUND 0x8000
> +#define LAST_BYTE(a) ((a) & ~(LOG_HEADER_FLAG_BUFFER_WRAPAROUND))
> +
> +/* MC and AIOP Magic words */
> +#define MAGIC_MC 0x4d430100
> +#define MAGIC_AIOP 0x41494F50
> +
> +struct log_header {
> + __le32 magic_word;
> + char reserved[4];
> + __le32 buf_start;
> + __le32 buf_length;
> + __le32 last_byte;
> +};
> +
> +struct console_data {
> + char *map_addr;
> + struct log_header *hdr;
> + char *start_addr;
> + char *end_addr;
> + char *end_of_data;
> + char *cur_ptr;
> +};
> +
> +struct resource mc_base_addr;
> +
> +static inline void adjust_end(struct console_data *cd)
> +{
> + u32 last_byte = readl(>hdr->last_byte);
> +
> + cd->end_of_data = cd->start_addr + LAST_BYTE(last_byte);
> +}
> +
> +static u64 get_mc_fw_base_address(void)
> +{
> + u64 mcfwbase = 0ULL;
> + u32 *mcfbaregs;
> +
> + mcfbaregs = (u32 *)ioremap(mc_base_addr.start,
> + resource_size(_base_addr));
> + if (!mcfbaregs) {
> + pr_err("could not map MC Firmaware Base registers\n");
> + return -EIO;
> + }
> +
> + mcfwbase = readl(mcfbaregs + MCFBAHR_OFFSET) & MC_FW_ADDR_MASK_HIGH;
> + mcfwbase <<= 32;
> + mcfwbase |= readl(mcfbaregs + MCFBALR_OFFSET) & MC_FW_ADDR_MASK_LOW;
> + iounmap(mcfbaregs);
> +
> + pr_debug("MC base address at 0x%016llx\n", mcfwbase);
> + return mcfwbase;
> +}
> +
> +static ssize_t dpaa2_console_size(struct console_data *cd)
> +{
> + ssize_t size;
> +
> + if
